Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10629532 | Integrated circuit structure having gate contact and method of forming same | Hui Zang | 2020-04-21 |
| 10593754 | SOI device structures with doped regions providing charge sinking | Jagar Singh, Jerome Ciavatti, Jae Gon Lee | 2020-03-17 |
| 10374029 | Semiconductor device resistor structure | Hui Zang, Shesh Mani Pandey | 2019-08-06 |
| 10217864 | Double gate vertical FinFET semiconductor structure | Hui Zang | 2019-02-26 |
| 10177037 | Methods of forming a CT pillar between gate structures in a semiconductor | Hui Zang | 2019-01-08 |
| 10170473 | Forming long channel FinFET with short channel vertical FinFET and related integrated circuit | Hui Zang, Yi Qi | 2019-01-01 |
| 10147648 | Vertical fin gate structure for RF device | Hui Zang | 2018-12-04 |
| 10128187 | Integrated circuit structure having gate contact and method of forming same | Hui Zang | 2018-11-13 |
| 10090209 | Methods of predicting unity gain frequency with direct current and/or low frequency parameters | Amit A. Dikshit, Tamilmani Ethirajan, Shrinivas J. Pandharpure, Vaidyanathan Subramanian | 2018-10-02 |
| 10079308 | Vertical transistor structure with looped channel | Shesh Mani Pandey, Hui Zang | 2018-09-18 |
| 10026740 | DRAM structure with a single diffusion break | Hui Zang, Jerome Ciavatti | 2018-07-17 |
| 9960077 | Ultra-scale gate cut pillar with overlay immunity and method for producing the same | Hui Zang, Ruilong Xie | 2018-05-01 |
| 9923046 | Semiconductor device resistor structure | Hui Zang, Shesh Mani Pandey | 2018-03-20 |
| 9704763 | Methods of predicting unity gain frequency with direct current and/or low frequency parameters | Amit A. Dikshit, Tamilmani Ethirajan, Shrinivas J. Pandharpure, Vaidyanathan Subramanian | 2017-07-11 |
| 9647145 | Method, apparatus, and system for increasing junction electric field of high current diode | Jagar Singh, Shesh Mani Pandey | 2017-05-09 |
| 9570538 | Methods of manufacturing polyresistors with selected TCR | Satyasuresh V. Choppalli, Prabhu R. Dattatreya | 2017-02-14 |
| 9472609 | Methods of manufacturing polyresistors with selected TCR | Satyasuresh V. Choppalli, Prabhu R. Dattatreya | 2016-10-18 |
| 9405186 | Sample plan creation for optical proximity correction with minimal number of clips | Amr Y. Abdo, Nathalie Casati, Maria Gabrani, James M. Oberschmidt, Ramya Viswanathan | 2016-08-02 |
| 8903697 | Solutions for modeling spatially correlated variations in an integrated circuit | Henry W. Trombley | 2014-12-02 |
| 8539426 | Method and system for extracting compact models for circuit simulation | Paul A. Hyde, Rainer Thoma | 2013-09-17 |
| 8524513 | Measuring floating body voltage in silicon-on-insulator (SOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) | Sourabh Khandelwal | 2013-09-03 |
| 8453101 | Method, system and program storage device for generating accurate performance targets for active semiconductor devices during new technology node development | James M. Johnson, Scott K. Springer, Rainer Thoma | 2013-05-28 |
| 8445961 | Measuring floating body voltage in silicon-on-insulator (SOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) | Sourabh Khandelwal | 2013-05-21 |
| 8417503 | System and method for target-based compact modeling | Kerry Bernstein, Richard Q. Williams | 2013-04-09 |
| 8010930 | Extracting consistent compact model parameters for related devices | Henry W. Trombley | 2011-08-30 |