Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12086594 | Vector friendly instruction format and execution thereof | Robert Valentine, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll, Santiago Galan Duran +14 more | 2024-09-10 |
| 11740904 | Vector friendly instruction format and execution thereof | Robert Valentine, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll, Santiago Galan Duran +14 more | 2023-08-29 |
| 11210096 | Vector friendly instruction format and execution thereof | Robert Valentine, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll, Santiago Galan Duran +14 more | 2021-12-28 |
| 11113053 | Data element comparison processors, methods, systems, and instructions | Asit K. Mishra, Edward T. Grochowski, Jonathan Pearce, Deborah T. Marr, Ehud Cohen +5 more | 2021-09-07 |
| 10795680 | Vector friendly instruction format and execution thereof | Robert Valentine, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll, Santiago Galan Duran +14 more | 2020-10-06 |
| 10445092 | Method and apparatus for performing a vector permute with an index and an immediate | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mark J. Charney, Milind B. Girkar, Bret L. Toll +4 more | 2019-10-15 |
| 10423411 | Data element comparison processors, methods, systems, and instructions | Asit K. Mishra, Edward T. Grochowski, Jonathan Pearce, Deborah T. Marr, Ehud Cohen +5 more | 2019-09-24 |
| 10296489 | Method and apparatus for performing a vector bit shuffle | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mark J. Charney, Guillem Sole, Roger Espasa | 2019-05-21 |
| 10296334 | Method and apparatus for performing a vector bit gather | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mark J. Charney, Guillem Sole, Roger Espasa | 2019-05-21 |
| 10255072 | Architectural register replacement for instructions that use multiple architectural registers | Mark J. Charney, Robert Valentine, Milind B. Girkar, Ashish Jha, Bret L. Toll +2 more | 2019-04-09 |
| 9785437 | Method and apparatus for performing a vector bit reversal and crossing | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mark J. Charney | 2017-10-10 |
| 9696992 | Apparatus and method for performing a check to optimize instruction flow | Robert N. Hanek, Warren E. Ferguson, Taraneh Bahrami, Avi A. Tevet, Dennis R. Bradford +2 more | 2017-07-04 |
| 9552205 | Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructions | Igor Ermolaev, Bret L. Toll, Robert Valentine, Gautam Doshi, Rama Kishan V. Malladi +1 more | 2017-01-24 |
| 9513917 | Vector friendly instruction format and execution thereof | Robert Valentine, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll, Santiago Galan Duran +14 more | 2016-12-06 |