HL

Hsiao-Ling Lu

UM United Microelectronics: 7 patents #808 of 4,560Top 20%
UI United Silicon Incorporated: 1 patents #20 of 57Top 40%
IBM: 1 patents #44,794 of 70,183Top 65%
Overall (All Time): #658,261 of 4,157,543Top 20%
8
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7544305 Chemical mechanical polishing process for forming shallow trench isolation structure Chia-Jung Hsu, Art Yu, Teng-Chun Tsai 2009-06-09
7294575 Chemical mechanical polishing process for forming shallow trench isolation structure Chia-Rung Hsu, Art Yu, Teng-Chun Tsai 2007-11-13
6913978 Method for forming shallow trench isolation structure Neng-Kuo Chen, Hsiu-Chuan Chu, Chih-An Huang, Teng-Chun Tsai 2005-07-05
6661097 Ti liner for copper interconnect with low-k dielectric Larry Clevenger, Stanley J. Klepeis, Jeffrey R. Marino, Andrew H. Simon, Yun-Yu Wang +2 more 2003-12-09
6251779 Method of forming a self-aligned silicide on a semiconductor wafer Li-Yeat Chen, Wen-Yi Hsieh 2001-06-26
6249138 Method for testing leakage current caused self-aligned silicide Michael W C Huang, Gwo-Shii Yang, Wen-Yi Hsieh 2001-06-19
6235606 Method of fabricating shallow trench isolation Michael W C Huang, Kuo-Tai Huang, Tri-Rung Yew 2001-05-22
6140192 Method for fabricating semiconductor device Michael Huang, Tri-Rung Yew 2000-10-31