HF

Harald D. Folberth

IBM: 21 patents #5,175 of 70,183Top 8%
Overall (All Time): #207,469 of 4,157,543Top 5%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11080456 Automated design closure with abutted hierarchy Michael A. Kazda, Paul G. Villarrubia, Stephan Held, Pietro Saccardi 2021-08-03
10831965 Placement of vectorized latches in hierarchical integrated circuit development Michael A. Kazda 2020-11-10
10616103 Constructing staging trees in hierarchical circuit designs Sven Nitzsche, Sven Peyer 2020-04-07
10534884 Layout of large block synthesis blocks in integrated circuits Harry Barowski, Joachim Keinert, Sourav Saha 2020-01-14
10417366 Layout of large block synthesis blocks in integrated circuits Harry Barowski, Joachim Keinert, Sourav Saha 2019-09-17
10366191 Layout of large block synthesis blocks in integrated circuits Harry Barowski, Joachim Keinert, Sourav Saha 2019-07-30
10242140 Layout of large block synthesis blocks in integrated circuits Harry Barowski, Joachim Keinert, Sourav Saha 2019-03-26
10235487 Layout of large block synthesis blocks in integrated circuits Harry Barowski, Joachim Keinert, Sourav Saha 2019-03-19
10223489 Placement clustering-based white space reservation Harry Barowski, Ajith Kumar M. Chandrasekaran, Joachim Keinert, Sourav Saha 2019-03-05
10169519 Area sharing between multiple large block synthesis (LBS) blocks Harry Barowski, Joachim Keinert, Sourav Saha 2019-01-01
10146899 Clock control trees Sven Nitzsche 2018-12-04
9946830 Area sharing between multiple large block synthesis (LBS) blocks Harry Barowski, Joachim Keinert, Sourav Saha 2018-04-17
9928329 Layout of large block synthesis blocks in integrated circuits Harry Barowski, Joachim Keinert, Sourav Saha 2018-03-27
9910948 Layout of large block synthesis blocks in integrated circuits Harry Barowski, Joachim Keinert, Sourav Saha 2018-03-06
9679101 Circuit placement with electro-migration mitigation Dilip Kumar, Sven Peyer, Sourav Saha, Hameedbasha Shaik 2017-06-13
9536037 Circuit placement with electro-migration mitigation Dilip Kumar, Sven Peyer, Sourav Saha, Hameedbasha Shaik 2017-01-03
9483601 Circuit routing based on total negative slack Sven Peyer, Sourav Saha 2016-11-01
9471741 Circuit routing based on total negative slack Sven Peyer, Sourav Saha 2016-10-18
9384316 Path-based congestion reduction in integrated circuit routing Sven Peyer, Sourav Saha 2016-07-05
6237128 Method and apparatus for enabling parallel layout checking of designing VLSI-chips Joachim Keinert, Jürgen Koehl, Kurt Pollmann, Oliver Rettig 2001-05-22
6043436 Wiring structure having rotated wiring layers J.o slashed.rgen Koehl, Bernhard Korte, Erich Klink 2000-03-28