Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12249541 | Vertical edge blocking (VEB) technique for increasing patterning process margin | Leonard P. GULER, Paul A. Nyhus, Elliot N. Tan, Charles H. Wallace | 2025-03-11 |
| 11594448 | Vertical edge blocking (VEB) technique for increasing patterning process margin | Leonard P. GULER, Paul A. Nyhus, Elliot N. Tan, Charles H. Wallace | 2023-02-28 |
| 9935205 | Internal spacers for nanowire transistors and method of fabrication thereof | Seiyon Kim, Daniel A. Simon, Nadia M. Rahhal-Orabi, Kelin J. Kuhn | 2018-04-03 |
| 9508796 | Internal spacers for nanowire transistors and method of fabrication thereof | Seiyon Kim, Daniel A. Simon, Nadia M. Rahhal-Orabi, Kelin J. Kuhn | 2016-11-29 |