Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11188696 | Method, system, and product for deferred merge based method for graph based analysis pessimism reduction | Sri Harsha POTHUKUCHI, Pradeep Yadav, Pawan Kulshreshtha, Igor Keller, Sharad Mehrotra +2 more | 2021-11-30 |
| 11144698 | Method, system, and product for an improved approach to placement and optimization in a physical design flow | Vibhor Garg, Edward J. Martinage, Krishna Belkhale | 2021-10-12 |
| 11003821 | Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuits | Sri Harsha POTHUKUCHI | 2021-05-11 |
| 10990733 | Shared timing graph propagation for multi-mode multi-corner static timing analysis | Vibhor Garg | 2021-04-27 |
| 10169501 | Timing context generation with multi-instance blocks for hierarchical analysis | Pawan Kulshreshtha | 2019-01-01 |
| 10133842 | Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designs | Pawan Kulshreshtha, Krishna Belkhale, Saulius Kersulis | 2018-11-20 |
| 10037394 | Hierarchical timing analysis for multi-instance blocks | Pawan Kulshreshtha | 2018-07-31 |
| 9529962 | System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design | Pradeep Yadav, Manuj Verma, Naresh Kumar, Prashant Sethia | 2016-12-27 |
| 9405882 | High performance static timing analysis system and method for input/output interfaces | Naresh Kumar, Prashant Sethia, Jeannette Sutherland, Shashank Tripathi | 2016-08-02 |
| 8863052 | System and method for generating and using a structurally aware timing model for representative operation of a circuit design | Naresh Kumar, Umesh Gupta, Pradeep Yadav, Prashant Sethia | 2014-10-14 |
| 8788995 | System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design | Naresh Kumar, Prashant Sethia, Krishna Belkhale | 2014-07-22 |