Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10831504 | Processor with hybrid pipeline capable of operating in out-of-order and in-order modes | Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Robert A. Shearer +1 more | 2020-11-10 |
| 10114652 | Processor with hybrid pipeline capable of operating in out-of-order and in-order modes | Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Robert A. Shearer +1 more | 2018-10-30 |
| 9971713 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +54 more | 2018-05-15 |
| 9354884 | Processor with hybrid pipeline capable of operating in out-of-order and in-order modes | Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Robert A. Shearer +1 more | 2016-05-31 |
| 9092347 | Allocating cache for use as a dedicated local storage | Miguel Comparan, Russell D. Hoover, Robert A. Shearer | 2015-07-28 |
| 9081501 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +55 more | 2015-07-14 |
| 9053037 | Allocating cache for use as a dedicated local storage | Miguel Comparan, Russell D. Hoover, Robert A. Shearer | 2015-06-09 |
| 9021237 | Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread | Miguel Comparan, Russell D. Hoover, Robert A. Shearer | 2015-04-28 |
| 8954973 | Transferring architected state between cores | Miguel Comparan, Russell D. Hoover, Robert A. Shearer | 2015-02-10 |
| 8949836 | Transferring architected state between cores | Miguel Comparan, Russell D. Hoover, Robert A. Shearer | 2015-02-03 |
| 8856602 | Multi-core processor with internal voting-based built in self test (BIST) | Jeffrey Douglas Brown, Miguel Comparan, Robert A. Shearer | 2014-10-07 |
| 8560924 | Register file soft error recovery | Bruce M. Fleischer, Thomas W. Fox, Charles D. Wait, Adam J. Muff | 2013-10-15 |
| 8082420 | Method and apparatus for executing instructions | Miguel Comparan, Brent F. Hilgart, Brian Lee Koehler, Eric O. Mejdrich, Adam J. Muff | 2011-12-20 |
| 7917703 | Network on chip that maintains cache coherency with invalidate commands | Miguel Comparan, Russell D. Hoover, Jamie R. Kuesel, Eric O. Mejdrich | 2011-03-29 |