Issued Patents All Time
Showing 1–25 of 106 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373286 | Handling non-correctable errors | David Matthew Thompson | 2025-07-29 |
| 12332790 | Multi-level cache security | David Matthew Thompson, Naveen Bhoria | 2025-06-17 |
| 12321277 | Prefetch management in a hierarchical cache system | Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Hung Ong | 2025-06-03 |
| 12321270 | Hardware coherence for memory controller | David Matthew Thompson, Naveen Bhoria | 2025-06-03 |
| 12271314 | Cache size change | Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2025-04-08 |
| 12197331 | Hardware coherence signaling protocol | David Matthew Thompson, Naveen Bhoria, Pete Michael Hippleheuser | 2025-01-14 |
| 12197332 | Memory pipeline control in a hierarchical memory system | Timothy David Anderson, Kai Chirca, David Matthew Thompson | 2025-01-14 |
| 12147301 | Parallelized scrubbing transactions | David Matthew Thompson | 2024-11-19 |
| 12141601 | Global coherence operations | Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2024-11-12 |
| 12135646 | Cache coherence shared state suppression | David Matthew Thompson, Timothy David Anderson, Kai Chirca | 2024-11-05 |
| 12086064 | Aliased mode for cache controller | Timothy David Anderson, Pramod Kumar Swami, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2024-09-10 |
| 12072824 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Kai Chirca, Matthew D. Pierson | 2024-08-27 |
| 12072812 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Kai Chirca, Naveen Bhoria +3 more | 2024-08-27 |
| 12056051 | Tag update bus for updated coherence state | David Matthew Thompson, Naveen Bhoria, Peter Michael Hippleheuser | 2024-08-06 |
| 12050914 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more | 2024-07-30 |
| 12045644 | Pseudo-random way selection | David Matthew Thompson | 2024-07-23 |
| 12038840 | Multi-level cache security | David Matthew Thompson, Naveen Bhoria | 2024-07-16 |
| 12019514 | Handling non-correctable errors | David Matthew Thompson | 2024-06-25 |
| 12014206 | Pipeline arbitration | David Matthew Thompson | 2024-06-18 |
| 12001351 | Multiple-requestor memory access pipeline and arbiter | David Matthew Thompson | 2024-06-04 |
| 12001282 | Write control for read-modify-write operations in cache memory | Timothy David Anderson, David Matthew Thompson, Daniel Wu | 2024-06-04 |
| 11977491 | Prefetch kill and revival in an instruction cache | Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Hung Ong | 2024-05-07 |
| 11940918 | Memory pipeline control in a hierarchical memory system | Timothy David Anderson, Kai Chirca, David Matthew Thompson | 2024-03-26 |
| 11921637 | Write streaming with cache write acknowledgment in a processor | Timothy David Anderson, David Matthew Thompson | 2024-03-05 |
| 11907753 | Controller with caching and non-caching modes | Timothy David Anderson, David Matthew Thompson | 2024-02-20 |