Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10860769 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Katherine H. Chiang, Chang-Yu Huang, Juan Chen, Ke-Wei Su, Chung-Kai Lin +2 more | 2020-12-08 |
| 10521538 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Katherine H. Chiang, Chang-Yu Huang, Juan Chen, Ke-Wei Su, Chung-Kai Lin +2 more | 2019-12-31 |
| 10216879 | Method for establishing aging model of device and analyzing aging state of device with aging model | Yi-Shun Huang, Wai-Kit Lee, Ya-Chin Liang, Juan Chen, Li-Chung Hsu +4 more | 2019-02-26 |
| 10019545 | Simulation scheme including self heating effect | Min-Chie Jeng, Chung-Kai Lin, Ke-Wei Su, Yi-Shun Huang, Ya-Chin Liang +2 more | 2018-07-10 |
| 9904743 | Method for analyzing interconnect process variation | Te-Yu Liu, Chia-Yi Chen, Wen-Cheng Huang, Ke-Wei Su, Ke-Ying Su +1 more | 2018-02-27 |
| 9558314 | Method of designing circuit layout and system for implementing the same | Te-Yu Liu, Ke-Ying Su, Chia-Yi Chen, Ke-Wei Su | 2017-01-31 |
| 7421383 | Method for extracting and modeling semiconductor device series resistance and for simulating a semiconductor device with use thereof | Ke-Wei Su, Jaw-Kang Her | 2008-09-02 |
| 7141485 | Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits | Ke-Wei Su, Jaw-Kang Her | 2006-11-28 |