Issued Patents All Time
Showing 126–150 of 168 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10096599 | Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process | Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park | 2018-10-09 |
| 10090304 | Isolation well doping with solid-state diffusion sources for FinFET architectures | Chia-Hong Jan, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L. Dias, Chanaka D. Munasinghe | 2018-10-02 |
| 10020313 | Antifuse with backfilled terminals | Chen-Guan Lee, Chia-Hong Jan | 2018-07-10 |
| 10008445 | Embedded fuse with conductor backfill | Chen-Guan Lee, Chia-Hong Jan | 2018-06-26 |
| 10002954 | Fin-based semiconductor devices and methods | Chia-Hong Jan | 2018-06-19 |
| 9972642 | High voltage three-dimensional devices having dielectric liners | Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti | 2018-05-15 |
| 9972616 | Methods of forming tuneable temperature coefficient FR embedded resistors | Chen-Guan Lee, Chia-Hong Jan | 2018-05-15 |
| 9947585 | Multi-gate transistor with variably sized fin | Nidhi Nidhi, Chia-Hong Jan, Roman W. Olac-Vaw, Hsu-Yu Chang, Neville L. Dias +1 more | 2018-04-17 |
| 9929090 | Antifuse element using spacer breakdown | Ting Chang, Chia-Hong Jan | 2018-03-27 |
| 9911815 | Extended-drain structures for high voltage field effect transistors | Nidhi Nidhi, Chia-Hong Jan | 2018-03-06 |
| 9899472 | Dielectric and isolation lower fin material for fin-based electronics | Chia-Hong Jan | 2018-02-20 |
| 9881927 | CMOS-compatible polycide fuse structure and method of fabricating same | Jeng-Ya David Yeh, Chia-Hong Jan, Joodong Park | 2018-01-30 |
| 9865695 | High-voltage transistor architectures, processes of forming same, and systems containing same | Chia-Hong Jan, Anisur Rahman | 2018-01-09 |
| 9842944 | Solid-source diffused junction for fin-based electronics | Chia-Hong Jan | 2017-12-12 |
| 9806095 | High voltage three-dimensional devices having dielectric liners | Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti | 2017-10-31 |
| 9799668 | Memory cell having isolated charge sites and method of fabricating same | Ting Chang, Chia-Hong Jan | 2017-10-24 |
| 9786783 | Transistor architecture having extended recessed spacer and source/drain regions and method of making same | Joodong Park, Jeng-Ya David Yeh, Chia-Hong Jan, Curtis Tsai | 2017-10-10 |
| 9780217 | Non-planar semiconductor device having self-aligned fin with top blocking layer | Jeng-Ya David Yeh, Chia-Hong Jan, Joodong Park | 2017-10-03 |
| 9748252 | Antifuse element utilizing non-planar topology | Chia-Hong Jan, Curtis Tsai, Joodong Park, Jeng-Ya David Yeh | 2017-08-29 |
| 9748327 | Pillar resistor structures for integrated circuitry | Chen-Guan Lee, Chia-Hong Jan | 2017-08-29 |
| 9741721 | Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM) | Joodong Park, Gopinath Bhimarasetti, Rahul Ramaswamy, Chia-Hong Jan, Jeng-Ya David Yeh +1 more | 2017-08-22 |
| 9570467 | High voltage three-dimensional devices having dielectric liners | Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti | 2017-02-14 |
| 9520494 | Vertical non-planar semiconductor device for system-on-chip (SoC) applications | Chia-Hong Jan, Curtis Tsai, Jeng-Ya David Yeh, Joodong Park | 2016-12-13 |
| 9502883 | Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection | Akm A. Ahsan | 2016-11-22 |
| 9356023 | Planar device on fin-based transistor architecture | Peter J. Vandervoorn, Chia-Hong Jan | 2016-05-31 |