Issued Patents All Time
Showing 201–225 of 245 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6552887 | Voltage dependent capacitor configuration for higher soft error rate tolerance | Tanay Karnik, Rajendran Nair | 2003-04-22 |
| 6545619 | Switched current source | Jaume A. Segura, Jose L. Rossello, Ali Keshavarzi, Siva G. Narendra | 2003-04-08 |
| 6529045 | NMOS precharge domino logic | Yibin Ye, Reed D. Spotten | 2003-03-04 |
| 6518796 | Dynamic CMOS circuits with individually adjustable noise immunity | Mircea R. Stan | 2003-02-11 |
| 6518817 | Voltage buffer | Jeremy R. Anderson, Siva G. Narendra | 2003-02-11 |
| 6518833 | Low voltage PVT insensitive MOSFET based voltage reference circuit | Siva G. Narendra, Krishnamurthy Soumyanath | 2003-02-11 |
| 6519176 | Dual threshold SRAM cell for single-ended sensing | Fatih Hamzaoglu, Ali Keshavarzi, Yibin Ye, Siva G. Narendra | 2003-02-11 |
| 6515513 | Reducing leakage currents in integrated circuits | Yibin Ye, James W. Tschanz | 2003-02-04 |
| 6496040 | Trading off gate delay versus leakage current using device stack effect | Siva G. Narendra, Yibin Ye | 2002-12-17 |
| 6496402 | Noise suppression for open bit line DRAM architectures | Dinesh Somasekhar, Shih-Lien Linus Lu | 2002-12-17 |
| 6492837 | Domino logic with output predischarge | Siva G. Narendra, Yibin Ye | 2002-12-10 |
| 6486706 | Domino logic with low-threshold NMOS pull-up | Yibin Ye, Siva G. Narendra | 2002-11-26 |
| 6484265 | Software control of transistor body bias in controlling chip parameters | Shekhar Y. Borkar, Ali Keshavarzi, Siva G. Narendra | 2002-11-19 |
| 6469572 | Forward body bias generation circuits based on diode clamps | David Bruneau, Siva G. Narendra | 2002-10-22 |
| 6459293 | Multiple parameter testing with improved sensitivity | Ali Keshavarzi, Kaushik Roy | 2002-10-01 |
| 6448840 | Adaptive body biasing circuit and method | James Kao, Siva G. Narendra, Rajendran Nair | 2002-09-10 |
| 6445216 | Sense amplifier having reduced Vt mismatch in input matched differential pair | David Bruneau, Siva G. Narendra | 2002-09-03 |
| 6433624 | Threshold voltage generation circuit | Vaughn J. Grossnickle, Siva G. Narendra | 2002-08-13 |
| 6429711 | Stack-based impulse flip-flop with stack node pre-charge and stack node pre-discharge | James W. Tschanz, Manoj Sachdev, Siva G. Narendra | 2002-08-06 |
| 6429726 | Robust forward body bias generation circuit with digital trimming for DC power supply variation | David Bruneau, Siva G. Narendra | 2002-08-06 |
| 6421269 | Low-leakage MOS planar capacitors for use within DRAM storage cells | Dinesh Somasekhar, Shih-Lien Linus Lu | 2002-07-16 |
| 6411156 | Employing transistor body bias in controlling chip parameters | Shekhar Y. Borkar, Ali Keshavarzi, Siva G. Narendra | 2002-06-25 |
| 6366156 | Forward body bias voltage generation systems | Siva G. Narendra, Shekhar Y. Borkar | 2002-04-02 |
| 6359802 | One-transistor and one-capacitor DRAM cell for logic process technology | Shih-Lien Linus Lu | 2002-03-19 |
| 6351156 | Noise reduction circuit | Fatih Hamzaoglu, Yibin Ye, Dinesh Somasekhar | 2002-02-26 |