Issued Patents All Time
Showing 151–175 of 245 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7030676 | Timing circuit for separate positive and negative edge placement in a switching DC-DC converter | Peter Hazucha, Gerhard Schrom, Tanay Karnik | 2006-04-18 |
| 7020041 | Method and apparatus to clamp SRAM supply voltage | Dinesh Somasekhar, Muhammad M. Khellah, Yibin Ye, James W. Tschanz, Stephen H. Tang | 2006-03-28 |
| 7015720 | Driver circuit | Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn | 2006-03-21 |
| 7015741 | Adaptive body bias for clock skew compensation | James W. Tschanz, Nasser A. Kurd, Siva G. Narendra, Javed S. Barkatullah | 2006-03-21 |
| 7001811 | Method for making memory cell without halo implant | Ali Keshavarzi, Stephen H. Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah +2 more | 2006-02-21 |
| 7002842 | Floating-body dynamic random access memory with purge line | Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah +2 more | 2006-02-21 |
| 6995605 | Resonance suppression circuit | Peter Hazucha, Jianping Xu, Gerhard Schrom, Tanay Karnik, Fabrice Paillet | 2006-02-07 |
| 6992339 | Asymmetric memory cell | Ali Keshavarzi, Stephen H. Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah +2 more | 2006-01-31 |
| 6992603 | Single-stage and multi-stage low power interconnect architectures | Maged Ghoneima, Peter Caputa, Muhammad M. Khellah, Ram Krishnamurthy, James W. Tschanz +2 more | 2006-01-31 |
| 6985380 | SRAM with forward body biasing to improve read cell stability | Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Ali R. Farhang, Gunjan H. Pandya | 2006-01-10 |
| 6975005 | Current reference apparatus and systems | Siva G. Narendra, Stephen H. Tang, Zachary Keer | 2005-12-13 |
| 6970018 | Clocked cycle latch circuit | Dejan Markovic, James W. Tschanz | 2005-11-29 |
| 6952376 | Method and apparatus to generate a reference value in a memory array | Dinesh Somasekhar, Yibin Ye, Muhammad M. Khellah, Fabrice Paillet, Stephen H. Tang +2 more | 2005-10-04 |
| 6917237 | Temperature dependent regulation of threshold voltage | James W. Tschanz, Mircea R. Stan, Siva G. Narendra | 2005-07-12 |
| 6909652 | SRAM bit-line reduction | Yibin Ye, Dinesh Somasekhar, Muhammad M. Khellah | 2005-06-21 |
| 6906973 | Bit-line droop reduction | Dinesh Somasekhar, Yibin Ye, Muhammad M. Khellah, Fabrice Paillet, Stephen H. Tang +2 more | 2005-06-14 |
| 6903984 | Floating-body DRAM using write word line for increased retention time | Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah +1 more | 2005-06-07 |
| 6879531 | Reduced read delay for single-ended sensing | Dinesh Somasekhar, Yibin Ye, Fatih Hamzaoglu | 2005-04-12 |
| 6876571 | Static random access memory having leakage reduction circuit | Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye | 2005-04-05 |
| 6870418 | Temperature and/or process independent current generation circuit | Stephen H. Tang, Siva G. Narendra | 2005-03-22 |
| 6849909 | Method and apparatus for weak inversion mode MOS decoupling capacitor | Rajendran Nair, Siva G. Narendra, Tanay Karnik | 2005-02-01 |
| 6831871 | Stable memory cell read | Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye | 2004-12-14 |
| 6828638 | Decoupling capacitors for thin gate oxides | Ali Keshavarzi, Tanay Karnik, Rajendran Nair | 2004-12-07 |
| 6825687 | Selective cooling of an integrated circuit for minimizing power loss | Ali Keshavarzi, Jaume A. Segura, Siva G. Narendra | 2004-11-30 |
| 6806739 | Time-borrowing N-only clocked cycle latch | Dejan Markovic, James W. Tschanz | 2004-10-19 |