VD

Vivek K. De

IN Intel: 241 patents #38 of 30,777Top 1%
Micron: 3 patents #3,077 of 6,345Top 50%
📍 Beaverton, OR: #8 of 3,140 inventorsTop 1%
🗺 Oregon: #36 of 28,073 inventorsTop 1%
Overall (All Time): #2,088 of 4,157,543Top 1%
245
Patents All Time

Issued Patents All Time

Showing 226–245 of 245 patents

Patent #TitleCo-InventorsDate
6346803 Current reference Vaughn J. Grossnickle, Siva G. Narendra 2002-02-12
6329874 Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode Yibin Ye 2001-12-11
6300819 Circuit including forward body bias from supply voltage and ground nodes Ali Keshavarzi, Siva G. Narendra, Shekhar Y. Borkar 2001-10-09
6300812 Process, voltage, and temperature insensitive two phase clock generation circuit Gregory E. Ruhl, Siva G. Narendra 2001-10-09
6275071 Domino logic circuit and method Yibin Ye, Siva G. Narendra 2001-08-14
6272666 Transistor group mismatch detection and reduction Shekhar Y. Borkar, Ali Keshavarzi, Siva G. Narendra 2001-08-07
6232827 Transistors providing desired threshold voltage and reduced short channel effects with forward body bias Ali Keshavarzi, Siva G. Narendra, Shekhar Y. Borkar 2001-05-15
6218895 Multiple well transistor circuits having forward body bias Ali Keshavarzi, Siva G. Narendra, Shekhar Y. Borkar 2001-04-17
6218892 Differential circuits employing forward body bias Krishnamurthy Soumyanath, Ali Keshavarzi, Shekhar Y. Borkar 2001-04-17
6191606 Method and apparatus for reducing standby leakage current using input vector activation Yibin Ye 2001-02-20
6181608 Dual Vt SRAM cell with bitline leakage control Ali Keshavarzi, Kevin X. Zhang, Yibin Ye 2001-01-30
6177788 Nonlinear body effect compensated MOSFET voltage reference Siva G. Narendra, Krishnamurthy Soumyanath 2001-01-23
6169419 Method and apparatus for reducing standby leakage current using a transistor stack effect Yibin Ye 2001-01-02
6166584 Forward biased MOS circuits 2000-12-26
6154045 Method and apparatus for reducing signal transmission delay using skewed gates Yibin Ye, Shih-Lien Linus Lu, Siva G. Narendra 2000-11-28
6100751 Forward body biased field effect transistor providing decoupling capacitance Ali Keshavarzi, Siva G. Narendra, Shekhar Y. Borkar 2000-08-08
6002272 Tri-rail domino circuit Dinesh Somasekhar 1999-12-14
5986476 Method and apparatus for implementing a dynamic adiabatic logic family 1999-11-16
5986473 Differential, mixed swing, tristate driver circuit for high performance and low power on-chip interconnects Ram Krishnamurthy, Krishnamurthy Soumyanath 1999-11-16
5841299 Method and apparatus for implementing an adiabatic logic family 1998-11-24