Issued Patents All Time
Showing 51–75 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7177987 | System and method for responses between different cache coherency protocols | Gregory Edward Tierney, Simon C. Steely, Jr. | 2007-02-13 |
| 7174431 | Mechanism for resolving ambiguous invalidates in a computer system | Gregory Edward Tierney | 2007-02-06 |
| 7149852 | System and method for blocking data responses | Gregory Edward Tierney, Simon C. Steely, Jr. | 2006-12-12 |
| 7143245 | System and method for read migratory optimization in a cache coherency protocol | Gregory Edward Tierney, Simon C. Steely, Jr. | 2006-11-28 |
| 7051163 | Directory structure permitting efficient write-backs in a shared memory computer system | Gregory Edward Tierney | 2006-05-23 |
| 7024520 | System and method enabling efficient cache line reuse in a computer system | Gregory Edward Tierney | 2006-04-04 |
| 7003635 | Generalized active inheritance consistency mechanism having linked writes | — | 2006-02-21 |
| 7000080 | Channel-based late race resolution mechanism for a computer system | Gregory Edward Tierney | 2006-02-14 |
| 6990559 | Mechanism for resolving ambiguous invalidates in a computer system | Gregory Edward Tierney | 2006-01-24 |
| 6961825 | Cache coherency mechanism using arbitration masks | Simon C. Steely, Jr., Madhumitra Sharma | 2005-11-01 |
| 6904465 | Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch | Simon C. Steely, Jr., Madhumitra Sharma | 2005-06-07 |
| 6898676 | Computer system supporting both dirty-shared and non-dirty-shared data processing entities | Gregory Edward Tierney | 2005-05-24 |
| 6895476 | Retry-based late race resolution mechanism for a computer system | Gregory Edward Tierney | 2005-05-17 |
| 6892290 | Linked-list early race resolution mechanism | — | 2005-05-10 |
| 6801986 | Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation | Simon C. Steely, Jr., Madhumitra Sharma | 2004-10-05 |
| 6636948 | Method and system for a processor to gain assured ownership of an up-to-date copy of data | Simon C. Steely, Jr., Madhu Sharna | 2003-10-21 |
| 6353876 | Cache memory exchange optimized memory organization for a computer system | Paul M. Goodwin | 2002-03-05 |
| 6286090 | Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches | Simon C. Steely, Jr., Madhumitra Sharma, Kourosh Gharachorloo | 2001-09-04 |
| 6256694 | Distributed early arbitration | David Fenwick, Denis Foley | 2001-07-03 |
| 6249846 | Distributed data dependency stall mechanism | Rahul Razdan | 2001-06-19 |
| 6209065 | Mechanism for optimizing generation of commit-signals in a distributed shared-memory system | Simon C. Steely, Jr., Kourosh Gharachorloo, Madhumitra Sharma | 2001-03-27 |
| 6202126 | Victimization of clean data blocks | Simon C. Steely, Jr., Madhumitra Sharma | 2001-03-13 |
| 6185654 | Phantom resource memory address mapping system | — | 2001-02-06 |
| 6125429 | Cache memory exchange optimized memory organization for a computer system | Paul M. Goodwin | 2000-09-26 |
| 6108737 | Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system | Madhumitra Sharma, Kourosh Gharachorloo, Simon C. Steely, Jr. | 2000-08-22 |