Issued Patents All Time
Showing 26–50 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8463987 | Scalable schedulers for memory controllers | Philip Abraham, Stanley S. Kulick | 2013-06-11 |
| 8281101 | Dynamic random access memory with shadow writes | Kuljit S. Bains | 2012-10-02 |
| 8010754 | Memory micro-tiling | James Akiyama, William H. Clifford | 2011-08-30 |
| 7990737 | Memory systems with memory chips down and up | — | 2011-08-02 |
| 7765366 | Memory micro-tiling | James Akiyama, William H. Clifford | 2010-07-27 |
| 7752411 | Chips providing single and consolidated commands | Shelley Chen | 2010-07-06 |
| 7673111 | Memory system with both single and consolidated commands | Shelley Chen | 2010-03-02 |
| 7519762 | Method and apparatus for selective DRAM precharge | — | 2009-04-14 |
| 7404055 | Memory transfer with early access to critical portion | Kuljit S. Bains, John B. Halbert, Greg Lemos | 2008-07-22 |
| 7386658 | Memory post-write page closing apparatus and method | Hemant G. Rotithor | 2008-06-10 |
| 7350030 | High performance chipset prefetcher for interleaved channels | Hemant G. Rotithor, Abhishek Singhal, Zohar Bogin, Raul Gutierrez, Buderya Acharya +1 more | 2008-03-25 |
| 7281079 | Method and apparatus to counter mismatched burst lengths | Kuljit S. Bains, John B. Halbert | 2007-10-09 |
| 7269088 | Identical chips with different operations in a system | — | 2007-09-11 |
| 7167946 | Method and apparatus for implicit DRAM precharge | — | 2007-01-23 |
| 7167947 | Memory post-write page closing apparatus and method | Hemant G. Rotithor | 2007-01-23 |
| 7127574 | Method and apparatus for out of order memory scheduling | Hemant G. Rotithor, Nagi Aboulenein | 2006-10-24 |
| 7006533 | Method and apparatus for hublink read return streaming | — | 2006-02-28 |
| 6983356 | High performance memory device-state aware chipset prefetcher | Hemant G. Rotithor, Donald W. McCauley | 2006-01-03 |
| 6978351 | Method and system to improve prefetching operations | Kenneth C. Creta, Joseph A. Bennett, Jasmin Ajanovic | 2005-12-20 |
| 6941425 | Method and apparatus for read launch optimizations in memory interconnect | — | 2005-09-06 |
| 6877052 | System and method for improved half-duplex bus performance | — | 2005-04-05 |
| 6842813 | Method and apparatus for single wire signaling of request types in a computer system having a point to point half duplex interconnect | David J. Harriman | 2005-01-11 |
| 6792496 | Prefetching data for peripheral component interconnect devices | Nagi Aboulenein | 2004-09-14 |
| 6785793 | Method and apparatus for memory access scheduling to reduce memory access latency | Nagi Aboulenein, Ram Huggahalli, Vamsee K. Madavarapu, Ken M. Crocker | 2004-08-31 |
| 6718512 | Dynamic parity inversion for I/O interconnects | Jasmin Ajanovic | 2004-04-06 |