RS

Raanan Sade

IN Intel: 100 patents #205 of 30,777Top 1%
📍 Sarid, OR: #1 of 1 inventorsTop 100%
Overall (All Time): #14,419 of 4,157,543Top 1%
100
Patents All Time

Issued Patents All Time

Showing 26–50 of 100 patents

Patent #TitleCo-InventorsDate
11816036 Method and system for performing data movement operations with read snapshot and in place write update Anil Vasudevan, Venkata Krishnan, Andrew J. Herdrich, Ren Wang, Robert G. Blankenship +7 more 2023-11-14
11809869 Systems and methods to store a tile register pair to memory Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke, Robert Valentine +5 more 2023-11-07
11789729 Systems and methods for computing dot products of nibbles in two tile operands Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke, Robert Valentine +4 more 2023-10-17
11748103 Systems and methods for performing matrix compress and decompress instructions Dan Baum, Michael Espig, James D. Guilford, Wajdi K. Feghali, Christopher J. Hughes +7 more 2023-09-05
11714648 Systems for performing instructions to quickly convert and use tiles as 1D vectors Bret L. Toll, Christopher J. Hughes, Dan Baum, Elmoustapha Ould-Ahmed-Vall, Robert Valentine +2 more 2023-08-01
11693785 Memory tagging apparatus and method Ron Gabor, Enrico Perla, Igor Yanover, Tomer Stark, Joseph Nuzman 2023-07-04
11675590 Systems and methods for performing instructions to transform matrices into row-interleaved format Robert Valentine, Bret L. Toll, Christopher J. Hughes, Alexander Heinecke, Elmoustapha Ould-Ahmed-Vall +1 more 2023-06-13
11669326 Systems, methods, and apparatuses for dot product operations Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke, Robert Valentine +5 more 2023-06-06
11656998 Memory tagging metadata manipulation Ron Gabor, Enrico Perla, Igor Yanover, Tomer Stark 2023-05-23
11645135 Hardware apparatuses and methods for memory corruption detection Tomer Stark, Ron Gabor, Joseph Nuzman, Bryant Bigbee 2023-05-09
11645077 Systems and methods to zero a tile register pair Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke, Robert Valentine +6 more 2023-05-09
11614936 Systems and methods for performing 16-bit floating-point matrix dot product instructions Alexander Heinecke, Robert Valentine, Mark J. Charney, Menachem Adelman, Zeev Sperber +2 more 2023-03-28
11609762 Systems and methods to load a tile register pair Simon Rubanovich, Amit Gradstein, Zeev Sperber, Alexander Heinecke, Robert Valentine +5 more 2023-03-21
11579880 Systems for performing instructions to quickly convert and use tiles as 1D vectors Bret L. Toll, Christopher J. Hughes, Dan Baum, Elmoustapha Ould-Ahmed-Vall, Robert Valentine +2 more 2023-02-14
11579883 Systems and methods for performing horizontal tile operations Christopher J. Hughes, Bret L. Toll, Dan Baum, Elmoustapha Ould-Ahmed-Vall, Robert Valentine +2 more 2023-02-14
11544062 Apparatus and method for store pairing with reduced hardware requirements Igor Yanover, Stanislav Shwartsman, Muhammad Taher, David Zysman, Liron Zur +1 more 2023-01-03
11507376 Systems for performing instructions for fast element unpacking into 2-dimensional registers Bret L. Toll, Alexander Heinecke, Christopher J. Hughes, Ronen Zohar, Michael Espig +4 more 2022-11-22
11500630 Apparatus and method for converting a floating-point value from half precision to single precision Robert Valentine, Mark J. Charney, Elmoustapha Ould-Ahmed-Vall, Jesus Corbal 2022-11-15
11455167 Efficient implementation of complex vector fused multiply add and complex vector multiply Thierry Pons, Amit Gradstein, Zeev Sperber, Mark J. Charney, Robert Valentine +1 more 2022-09-27
11403071 Systems and methods for performing instructions to transpose rectangular tiles Robert Valentine, Mark J. Charney, Simon Rubanovich, Amit Gradstein, Zeev Sperber +5 more 2022-08-02
11392380 Apparatuses, methods, and systems to precisely monitor memory store accesses Ahmad Yasin, Liron Zur, Igor Yanover, Joseph Nuzman 2022-07-19
11392503 Memory tagging apparatus and method Ron Gabor, Igor Yanover, Assaf Zaltsman, Tomer Stark 2022-07-19
11392381 Systems and methods for performing instructions to transform matrices into row-interleaved format Robert Valentine, Bret L. Toll, Christopher J. Hughes, Alexander Heinecke, Elmoustapha Ould-Ahmed-Vall +1 more 2022-07-19
11372643 Systems and methods for performing instructions to convert to 16-bit floating-point format Alexander Heinecke, Robert Valentine, Mark J. Charney, Menachem Adelman, Zeev Sperber +2 more 2022-06-28
11366663 Systems and methods for performing 16-bit floating-point vector dot product instructions Alexander Heinecke, Robert Valentine, Mark J. Charney, Menachem Adelman, Zeev Sperber +2 more 2022-06-21