MH

Michael L. Hattendorf

IN Intel: 85 patents #269 of 30,777Top 1%
UI University Of Illinois: 1 patents #1,166 of 3,009Top 40%
📍 Portland, OR: #153 of 9,213 inventorsTop 2%
🗺 Oregon: #284 of 28,073 inventorsTop 2%
Overall (All Time): #19,417 of 4,157,543Top 1%
86
Patents All Time

Issued Patents All Time

Showing 76–86 of 86 patents

Patent #TitleCo-InventorsDate
8896030 Integrated circuits with selective gate electrode recess Srijit Mukherjee, Christopher J. Wiegand, Tyler J. Weeks, Mark Liu 2014-11-25
8426858 Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain Jack Hwang, Anand S. Murthy, Andrew N. Westmeyer 2013-04-23
7858981 Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain Jack Hwang, Anand S. Murthy, Andrew N. Westmeyer 2010-12-28
7812394 CMOS transistor junction regions formed by a CVD etching and deposition sequence Anand S. Murthy, Glenn A. Glass, Andrew N. Westmeyer, Jeffrey R. Wank 2010-10-12
7678631 Formation of strain-inducing films Anand S. Murthy, Glenn A. Glass 2010-03-16
7595248 Angled implantation for removal of thin film layers Justin K. Brask, Justin S. Sandford, Jack T. Kavalieros, Matthew V. Metz 2009-09-29
7479432 CMOS transistor junction regions formed by a CVD etching and deposition sequence Anand S. Murthy, Glenn A. Glass, Andrew N. Westmeyer, Jeffrey R. Wank 2009-01-20
7479431 Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain Jack Hwang, Anand S. Murthy, Andrew N. Westmeyer 2009-01-20
7402872 Method for forming an integrated circuit Anand S. Murthy, Glenn A. Glass, Andrew N. Westmeyer, Tahir Ghani 2008-07-22
7195985 CMOS transistor junction regions formed by a CVD etching and deposition sequence Anand S. Murthy, Glenn A. Glass, Andrew N. Westmeyer, Jeffrey R. Wank 2007-03-27
6103614 Hydrogen ambient process for low contact resistivity PdGe contacts to III-V materials David Ahmari, David F. Lemmerhirt, Gregory E. Stillman 2000-08-15