Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
HN

Hang T. Nguyen

Intel: 43 patents #789 of 30,777Top 3%
Disney: 8 patents #911 of 6,686Top 15%
BHBaker Hughes Holdings: 2 patents #1,327 of 3,522Top 40%
ATAreal Technology: 1 patents #3 of 12Top 25%
BOBaker Hughes Oilfield Operations: 1 patents #478 of 1,057Top 50%
BTBaker Oil Tools: 1 patents #43 of 87Top 50%
Tempe, AZ: #18 of 2,648 inventorsTop 1%
Arizona: #361 of 32,909 inventorsTop 2%
Overall (All Time): #44,590 of 4,157,543Top 2%
56 Patents All Time

Issued Patents All Time

Showing 26–50 of 56 patents

Patent #TitleCo-InventorsDate
7464227 Method and apparatus for supporting opportunistic sharing in coherent multiprocessors Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven Tu 2008-12-09
7464208 Method and apparatus for shared resource management in a multiprocessing system Steven Tu 2008-12-09
7428607 Apparatus and method for arbitrating heterogeneous agents in on-chip busses Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven Tu 2008-09-23
7415633 Method and apparatus for preventing and recovering from TLB corruption by soft error Sujat Jamil 2008-08-19
7406552 Systems and methods for early fixed latency subtractive decoding including speculative acknowledging Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven Tu 2008-07-29
7406553 System and apparatus for early fixed latency subtractive decoding Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven Tu 2008-07-29
7366845 Pushing of clean data to one or more processors in a system having a coherency protocol Sujat Jamil, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu 2008-04-29
7360007 System including a segmentable, shared bus Samantha J. Edirisooriya 2008-04-15
7353317 Method and apparatus for implementing heterogeneous interconnects Samantha J. Edirisooriya, Steven Tu, Gregory Tse, Sujat Jamil, David E. Miner +1 more 2008-04-01
7219176 System and apparatus for early fixed latency subtractive decoding Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven Tu 2007-05-15
7216252 Method and apparatus for machine check abort handling in a multiprocessing system Steven Tu 2007-05-08
7194671 Mechanism handling race conditions in FRC-enabled processors Steven Tu, Alexander J. Honcharik, Sujat Jamil, Quinn W. Merrell 2007-03-20
7159077 Direct processor cache access within a system having a coherent multi-processor protocol Steven Tu, Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness 2007-01-02
7143220 Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven Tu 2006-11-28
7124224 Method and apparatus for shared resource management in a multiprocessing system Steven Tu 2006-10-17
7100001 Methods and apparatus for cache intervention Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven Tu +1 more 2006-08-29
7062613 Methods and apparatus for cache intervention Sujat Jamil, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu 2006-06-13
7055060 On-die mechanism for high-reliability processor Steven Tu, Alexander J. Honcharik, Sujat Jamil 2006-05-30
7003632 Method and apparatus for scalable disambiguated coherence in shared storage hierarchies Sujat Jamil, Quinn W. Merrell 2006-02-21
6983348 Methods and apparatus for cache intervention Sujat Jamil, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven Tu 2006-01-03
6954886 Deterministic hardware reset for FRC machine Steven Tu 2005-10-11
6684346 Method and apparatus for machine check abort handling in a multiprocessing system Steven Tu 2004-01-27
6658621 System and method for silent data corruption prevention due to next instruction pointer corruption by soft errors Sujat Jamil, Andres Rabago 2003-12-02
6651145 Method and apparatus for scalable disambiguated coherence in shared storage hierarchies Sujat Jamil, Quinn W. Merrell 2003-11-18
6615366 Microprocessor with dual execution core operable in high reliability mode Edward T. Grochowski, William C. Rash, Nhon Quach, Andres Rabago 2003-09-02