Issued Patents All Time
Showing 26–50 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9426183 | Authentication policy orchestration for a user device | Nahal Shahidzadeh | 2016-08-23 |
| 9262173 | Critical section detection and prediction mechanism for hardware lock elision | Ravi Rajwar, Srikanth Srinivasan | 2016-02-16 |
| 8683143 | Unbounded transactional memory systems | Ali-Reza Adl-Tabatabai, Bratin Saha, Ravi Rajwar | 2014-03-25 |
| 8627030 | Late lock acquire mechanism for hardware lock elision (HLE) | Ravi Rajwar, Srikanth Srinivasan | 2014-01-07 |
| 8190859 | Critical section detection and prediction mechanism for hardware lock elision | Ravi Rajwar, Srikanth Srinivasan | 2012-05-29 |
| 8180977 | Transactional memory in out-of-order processors | Ravi Rajwar, Konrad K. Lai | 2012-05-15 |
| 8180967 | Transactional memory virtualization | Ravi Rajwar, Konrad K. Lai | 2012-05-15 |
| 7900023 | Technique to enable store forwarding during long latency instruction execution | Ravi Rajwar, Srikanth Srinivasan, Amit Gandhi | 2011-03-01 |
| 7809903 | Coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions | Ali-Reza Adl-Tabatabai, Bratin Saha, Richard L. Hudson, Ravi Rajwar | 2010-10-05 |
| 7752423 | Avoiding execution of instructions in a second processor by committing results obtained from speculative execution of the instructions in a first processor | Sebastien Hily | 2010-07-06 |
| 7711932 | Scalable rename map table recovery | Ravi Rajwar, Srikanth Srinivasan | 2010-05-04 |
| 7487337 | Back-end renaming in a continual flow processor pipeline | Ravi Rajwar, Srikanth Srinivasan | 2009-02-03 |
| 7418552 | Memory disambiguation for large instruction windows | Sebastien Hily | 2008-08-26 |
| 7363477 | Method and apparatus to reduce misprediction penalty by exploiting exact convergence | Srikanth Srinivasan, Amit Gandhi | 2008-04-22 |
| 6772324 | Processor having multiple program counters and trace buffers outside an execution pipeline | Kingsum Chow | 2004-08-03 |
| 6697912 | Prioritized content addressable memory | — | 2004-02-24 |
| 6643733 | Prioritized content addressable memory | — | 2003-11-04 |
| 6591342 | Memory disambiguation for large instruction windows | Sebastien Hily | 2003-07-08 |
| 6493791 | Prioritized content addressable memory | — | 2002-12-10 |
| 6493820 | Processor having multiple program counters and trace buffers outside an execution pipeline | Kingsum Chow | 2002-12-10 |
| 6463522 | Memory system for ordering load and store instructions in a processor that performs multithread execution | — | 2002-10-08 |
| 6378062 | Method and apparatus for performing a store operation | Jeffery M. Abramson, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland | 2002-04-23 |
| 6247121 | Multithreading processor with thread predictor | Quinn A. Jacobson | 2001-06-12 |
| 6240509 | Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation | — | 2001-05-29 |
| 6182210 | Processor having multiple program counters and trace buffers outside an execution pipeline | Kingsum Chow | 2001-01-30 |