Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6202125 | Processor-cache protocol using simple commands to implement a range of cache configurations | Dan Patterson, Bindi A. Prasad, Peter D. MacWilliams, Steve Hunt, Phil Gi Lee | 2001-03-13 |
| 6118306 | Changing clock frequency | John T. Orton, Cau L. Nguyen, Xia Dai, Raviprakash Nagaraj, Edwin J. Pole, II | 2000-09-12 |
| 6006299 | Apparatus and method for caching lock conditions in a multi-processor system | Wen-Hann Wang, Konrad K. Lai, Mandar Joshi, Nitin V. Sarangdhar, Matthew A. Fisch | 1999-12-21 |
| 5966722 | Method and apparatus for controlling multiple dice with a single die | Konrad K. Lai | 1999-10-12 |
| 5937171 | Method and apparatus for performing deferred transactions | Nitin V. Sarangdhar, Konrad K. Lai, Peter D. MacWilliams | 1999-08-10 |
| 5923857 | Method and apparatus for ordering writeback data transfers on a bus | Stephen S. Pawlowski, Peter D. MacWilliams, Nitin V. Sarangdhar | 1999-07-13 |
| 5911053 | Method and apparatus for changing data transfer widths in a computer system | Stephen S. Pawlowski, Peter D. MacWilliams | 1999-06-08 |
| 5903908 | Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories | Konrad K. Lai, Michael W. Rodehamel | 1999-05-11 |
| 5903738 | Method and apparatus for performing bus transactions in a computer system | Nitin V. Sarangdhar, Konrad K. Lai | 1999-05-11 |
| 5832534 | Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories | Konrad K. Lai, Michael W. Rhodehamel | 1998-11-03 |
| 5809524 | Method and apparatus for cache memory replacement line identification | Wen-Hann Wang, Michael W. Rhodehamel, John M. Bauer, Nitin V. Sarangdhar | 1998-09-15 |
| 5796977 | Highly pipelined bus architecture | Nitin V. Sarangdhar, Konrad K. Lai, Stephen S. Pawlowski, Peter D. MacWilliams, Michael W. Rhodehamel | 1998-08-18 |
| 5754833 | Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratio | Michael W. Rhodehamel | 1998-05-19 |
| 5715428 | Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system | Wen-Hann Wang, Konrad K. Lai, Michael W. Rhodehamel, Nitin V. Sarangdhar, John M. Bauer +2 more | 1998-02-03 |
| 5701503 | Method and apparatus for transferring information between a processor and a memory system | Wen-Hann Wang, Michael W. Rhodehamel, John M. Bauer, Nitin V. Sarangdhar | 1997-12-23 |
| 5678020 | Memory subsystem wherein a single processor chip controls multiple cache memory chips | Konrad K. Lai | 1997-10-14 |
| 5615343 | Method and apparatus for performing deferred transactions | Nitin V. Sarangdhar, Konrad K. Lai, Peter D. MacWilliams, Stephen S. Pawlowski, Michael W. Rhodehamel | 1997-03-25 |
| 5581782 | Computer system with distributed bus arbitration scheme for symmetric and priority agents | Nitin V. Sarangdhar, Konrad K. Lai, Michael W. Rhodehamel, Matthew A. Fisch | 1996-12-03 |
| 5568620 | Method and apparatus for performing bus transactions in a computer system | Nitin V. Sarangdhar, Konrad K. Lai | 1996-10-22 |
| 5345576 | Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss | Phillip G. Lee, Eileen Riggs, Randy Steck | 1994-09-06 |
| 4803622 | Programmable I/O sequencer for use in an I/O processor | William L. Bain, Jr., Robert Bedichek, George W. Cox, Gerhard Grassl, Craig B. Peterson +2 more | 1989-02-07 |