GP

Gerald George Pechanek

IN Intel: 65 patents #432 of 30,777Top 2%
IBM: 33 patents #2,996 of 70,183Top 5%
PT Pts: 23 patents #1 of 123Top 1%
BO Bops: 16 patents #1 of 12Top 9%
BS Billions Of Operations Per Second: 8 patents #1 of 11Top 10%
📍 Cary, NC: #13 of 3,681 inventorsTop 1%
🗺 North Carolina: #50 of 45,564 inventorsTop 1%
Overall (All Time): #5,345 of 4,157,543Top 1%
161
Patents All Time

Issued Patents All Time

Showing 126–150 of 161 patents

Patent #TitleCo-InventorsDate
6167502 Method and apparatus for manifold array processing Nikos P. Pitsianis, Edwin Frank Barry, Thomas L. Drabenstott 2000-12-26
6151668 Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication Thomas L. Drabenstott, Juan Guillermo Revilla, David Strube, Grayson Morris 2000-11-21
6128720 Distributed processing array with component processors performing customized interpretation of instructions Larry D. Larsen, Clair John Glossner, III, Stamatis Vassiliaadis 2000-10-03
6101592 Methods and apparatus for scalable instruction set architecture with dynamic compact instructions Edwin Frank Barry, Juan Guillermo Revilla, Larry D. Larsen 2000-08-08
6041398 Massively parallel multiple-folded clustered processor mesh array Stamatis Vassiliadis, Jose G. Delgado-Frias 2000-03-21
6023753 Manifold array processor Charles W. Kurak, Jr. 2000-02-08
5784632 Parallel diagonal-fold array processor Stamatis Vassiliadis, Jose G. Delgado-Frias 1998-07-21
5682491 Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier Larry D. Larsen, Clair John Glossner, III, Stamatis Vassiliaadis, Daniel H. McCabe 1997-10-28
5682544 Massively parallel diagonal-fold tree array processor Stamatis Vassiliadis, Jose G. Delgado-Frias 1997-10-28
5659785 Array processor communication architecture with broadcast processor instructions Larry D. Larsen, Clair John Glossner, III, Stamatis Vassiliaadis 1997-08-19
5649135 Parallel processing system and method using surrogate instructions Clair John Glossner, III, Larry D. Larsen, Stamatis Vassiliadis 1997-07-15
5640586 Scalable parallel group partitioned diagonal-fold switching tree computing apparatus Stamatis Vassiliadis, Jose G. Delgado-Frias 1997-06-17
5617512 Triangular scalable neural array processor Stamatis Vassiliadis 1997-04-01
5612908 Processing element for parallel array processor Stamatis Vassiliadis, Jose G. Delgado-Frias 1997-03-18
5613044 Learning machine synapse processor system apparatus Stamatis Vassiliadis, Jose G. Delgado-Frias 1997-03-18
5577262 Parallel array processor interconnections Stamatis Vassiliadis, Jose G. Delgado-Fnias 1996-11-19
5546336 Processor using folded array structures for transposition memory and fast cosine transform computation Stamatis Vassiliadis 1996-08-13
5542026 Triangular scalable neural array processor Stamatis Vassiliadis 1996-07-30
5517596 Learning machine synapse processor system apparatus Stamatis Vassiliadis, Jose G. Delgado-Frias 1996-05-14
5509106 Triangular scalable neural array processor Stamatis Vassiliadis 1996-04-16
5483620 Learning machine synapse processor system apparatus Stamatis Vassiliadis, Jose G. Delgado-Frias 1996-01-09
5337395 SPIN: a sequential pipeline neurocomputer Stamatis Vassiliadis, Jose G. Delgado-Frias 1994-08-09
5329611 Scalable flow virtual learning neurocomputer Stamatis Vassiliadis, Jose G. Delgado-Frias 1994-07-12
5325464 Pyramid learning architecture neurocomputer Stamatis Vassiliadis, Jose G. Delgado-Frias 1994-06-28
5251287 Apparatus and method for neural processing Stamatis Vassiliadis 1993-10-05