Issued Patents All Time
Showing 51–75 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9048889 | High-speed data communications architecture | Divya Vijayaraghavan, Gregg William Baeckler | 2015-06-02 |
| 9041431 | Partial reconfiguration and in-system debugging | Alan L. Herrmann | 2015-05-26 |
| 8943393 | Distributed burst error protection | Gregg William Baeckler | 2015-01-27 |
| 8935645 | Reconfigurable logic block | Gary Lai, Lu Zhou, Bruce B. Pedersen | 2015-01-13 |
| 8886856 | Methods and apparatus for communicating low-latency word category over multi-lane link | — | 2014-11-11 |
| 8856711 | Apparatus and methods for time-multiplex field-programmable gate arrays | Sinan Kaptanoglu | 2014-10-07 |
| 8810299 | Signal flow control through clock signal rate adjustments | Gregg William Baeckler | 2014-08-19 |
| 8806249 | Systems and methods for reducing static and total power consumption in programmable logic device architectures | — | 2014-08-12 |
| 8775894 | Lane specific CRC | Gregg William Baeckler | 2014-07-08 |
| 8751998 | Method and system for partial reconfiguration simulation | Marwan A. Khalaf, Renxin Xia | 2014-06-10 |
| 8692595 | Transceiver circuitry with multiple phase-locked loops | Sergey Shumarayev, Ramanand Venkata | 2014-04-08 |
| 8686753 | Partial reconfiguration and in-system debugging | Alan L. Herrmann | 2014-04-01 |
| 8638245 | Method and system for dynamic table line encoding | Gregg William Baeckler | 2014-01-28 |
| 8572538 | Reconfigurable logic block | Gary Lai, Lu Zhou, Bruce B. Pedersen | 2013-10-29 |
| 8543955 | Apparatus and methods for time-multiplex field-programmable gate arrays | Sinan Kaptanoglu | 2013-09-24 |
| 8488729 | Deskew across high speed data lanes | Brent A. Fairbanks, Ning Xue | 2013-07-16 |
| 8436646 | Reconfigurable logic block with user RAM | Triet Nguyen, Lu Zhou, Gary Lai | 2013-05-07 |
| 8355477 | Multi-lane communication with measurable latency | — | 2013-01-15 |
| 8225259 | Apparatus and methods for time-multiplex field-programmable gate arrays with multiple clocks | Sinan Kaptanoglu | 2012-07-17 |
| 8156355 | Systems and methods for reducing static and total power consumption | Vaughn Betz | 2012-04-10 |
| 8001499 | Circuit type pragma for computer aided design tools | Greg William Baeckler, Michael D. Hutton | 2011-08-16 |
| 7839167 | Interconnection and input/output resources for programmable logic integrated circuit devices | Tony Ngai, Bruce B. Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang +6 more | 2010-11-23 |
| 7594208 | Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage | Terry Borer, Ian Chesal, James Schleicher, Mike Hutton, Boris Ratchev +7 more | 2009-09-22 |
| 7509618 | Method and apparatus for facilitating an adaptive electronic design automation tool | Michael D. Hutton, Yean-Yow Hwang | 2009-03-24 |
| 7492188 | Interconnection and input/output resources for programmable logic integrated circuit devices | Tony Ngai, Bruce B. Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang +6 more | 2009-02-17 |