Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6760031 | Upgrading an integrated graphics subsystem | Thomas A. Piazza | 2004-07-06 |
| 6734862 | Memory controller hub | James Chapple, Tom Dever, Cass A. Blodgett, Bryan R. White, David Puffer | 2004-05-11 |
| 6725349 | Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory | James M. Dodd, Nicholas D. Wade | 2004-04-20 |
| 6630936 | Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (BLT) in parallel | — | 2003-10-07 |
| 6624817 | Symmetrical accelerated graphics port (AGP) | — | 2003-09-23 |
| 6535956 | Method and apparatus for automatically detecting whether a board level cache is implemented with Mcache | James M. Dodd | 2003-03-18 |
| 6505282 | Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics | James M. Dodd, Nicholas D. Wade | 2003-01-07 |
| 6470238 | Method and apparatus to control device temperature | Puthiya K. Nizar, David J. McDonnell, Michael G. LaTondre, Jeff Rabe, Tom A. Sutera +2 more | 2002-10-22 |
| 6442632 | System resource arbitration mechanism for a host bridge | George R. Hayek, Aniruddha Kundu, Gary Solomon, Peter D. MacWilliams, James M. Dodd | 2002-08-27 |
| 6313766 | Method and apparatus for accelerating software decode of variable length encoded information | Brian J. Tucker | 2001-11-06 |
| 6212589 | System resource arbitration mechanism for a host bridge | George R. Hayek, Aniruddha Kundu, Gary Solomon, Peter D. MacWilliams, James M. Dodd | 2001-04-03 |
| 6115796 | Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions | George R. Hayek, Ali S. Oztaskin, Bruce A. Young | 2000-09-05 |
| 6097402 | System and method for placement of operands in system memory | Colyn S. Case, George R. Hayek, Kim A. Meinerth | 2000-08-01 |
| 6092158 | Method and apparatus for arbitrating between command streams | David J. Harriman, Jasmin Ajanovic | 2000-07-18 |
| 6088772 | Method and apparatus for improving system performance when reordering commands | David J. Harriman, Jasmin Ajanovic | 2000-07-11 |
| 6047334 | System for delaying dequeue of commands received prior to fence command until commands received before fence command are ordered for execution in a fixed sequence | David J. Harriman, Robert J. Riesenman | 2000-04-04 |
| 5990913 | Method and apparatus for implementing a flush command for an accelerated graphics port device | David J. Harriman | 1999-11-23 |
| 5974571 | Method and apparatus for avoiding deadlock in the issuance of commands that are reordered and require data movement according to an original command order | Robert J. Riesenman, David J. Harriman | 1999-10-26 |
| 5918025 | Method and apparatus for converting a five wire arbitration/buffer management protocol into a two wire protocol | George R. Hayek, Jasmin Ajanovic, Rajeev Prasad | 1999-06-29 |
| 5911051 | High-throughput interconnect allowing bus transactions based on partial access requests | David G. Carson, George R. Hayek, Brent S. Baxter, Colyn S. Case, Kim A. Meinerth | 1999-06-08 |
| 5898856 | Method and apparatus for automatically detecting a selected cache type | James M. Dodd | 1999-04-27 |
| 5860112 | Method and apparatus for blending bus writes and cache write-backs to memory | Michael N. Derr | 1999-01-12 |
| 5809228 | Method and apparatus for combining multiple writes to a memory resource utilizing a write buffer | Michael N. Derr | 1998-09-15 |
| 5740385 | Low load host/PCI bus bridge | George R. Hayek, Aniruddha Kundu, Kuljit S. Bains, Gary Solomon | 1998-04-14 |
| 5737746 | Computer system including an apparatus for reducing power consumption in an on-chip tag static RAM | Jennefer S. Hardin, Robert F. Kubick | 1998-04-07 |