Issued Patents All Time
Showing 451–475 of 488 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10078590 | Technique to share information among different cache coherency domains | Zeev Offen, Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Opher Kahn | 2018-09-18 |
| 10062429 | System, apparatus and method for segmenting a memory array | Bhushan M. Borole, Iqbal Rajwani, Anupama A. Thaploo, Sunil Nekkanti, Abhisek R. Appu | 2018-08-28 |
| 10043232 | Compute cluster preemption within a general-purpose graphics processing unit | Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite +4 more | 2018-08-07 |
| 10013734 | Programmable controller and command cache for graphics processors | Jeffery S. Boles, Hema Chand Nalluri, Balaji Vembu, Michael Apodaca, Lalit K. Saptarshi | 2018-07-03 |
| 9946650 | Technique to share information among different cache coherency domains | Zeev Offen, Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Opher Kahn | 2018-04-17 |
| 9928170 | Scatter/gather capable system coherent cache | Thomas A. Piazza, Murali Sundaresan | 2018-03-27 |
| 9916257 | Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory | Rajesh M. Sankaran, Philip R. Lantz, Asit K. Mallick, James B. Crossland, Aditya Navale +2 more | 2018-03-13 |
| 9886934 | Ordering mechanism for offload graphics scheduling | Bryan R. White, Balaji Vembu, Murali Ramadoss, Aditya Navale | 2018-02-06 |
| 9805438 | Dynamically rebalancing graphics processor resources | Nikos Kaburlasos, Eric C. Samson | 2017-10-31 |
| 9779473 | Memory mapping for a graphics processing unit | Balaji Vembu, Murali Ramadoss, Aditya Navale | 2017-10-03 |
| 9678795 | Direct ring 3 submission of processing jobs to adjunct processors | Aditya Navale, Balaji Vembu, Murali Ramadoss | 2017-06-13 |
| 9665488 | Technique to share information among different cache coherency domains | Zeev Offen, Ariel Berkovits, Thomas A. Piazza, Robert L. Farrell, Opher Kahn | 2017-05-30 |
| 9626735 | Page management approach to fully utilize hardware caches for tiled rendering | Aditya Navale | 2017-04-18 |
| 9626732 | Supporting atomic operations as post-synchronization operations in graphics processing architectures | Hema Chand Nalluri, Aditya Navale | 2017-04-18 |
| 9619855 | Scalable geometry processing within a checkerboard multi-GPU configuration | Peter L. Doyle, Jeffery S. Boles, Arthur D. Hunter Jr., Aditya Navale | 2017-04-11 |
| 9612833 | Handling compressed data over distributed cache fabric | Hong Jiang, James M. Holland | 2017-04-04 |
| 9542336 | Isochronous agent data pinning in a multi-level memory system | Marc Torrant, David Puffer, Blaise Fanning, Bryan R. White, Joydeep Ray +3 more | 2017-01-10 |
| 9471323 | System and method of using an atomic data buffer to bypass a memory location | Jayakrishna P S, Pattabhiraman K | 2016-10-18 |
| 9471492 | Scatter/gather capable system coherent cache | Thomas A. Piazza, Murali Sundaresan | 2016-10-18 |
| 9436972 | System coherency in a distributed graphics processor hierarchy | Aditya Navale | 2016-09-06 |
| 9396513 | Using group page fault descriptors to handle context switches and process terminations in graphics processors | — | 2016-07-19 |
| 9390462 | Memory mapping for a graphics processing unit | Balaji Vembu, Murali Ramadoss, Aditya Navale | 2016-07-12 |
| 9330433 | Data distribution fabric in scalable GPUs | Lakshminarayanan Striramassarma, Akif Ali | 2016-05-03 |
| 9323684 | Dynamic cache and memory allocation for memory subsystems | Aditya Navale | 2016-04-26 |
| 9268691 | Fast mechanism for accessing 2n±1 interleaved memory system | Saurabh Sharma, Aditya Navale | 2016-02-23 |