Issued Patents All Time
Showing 126–150 of 153 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5681769 | Method of fabricating a high capacitance insulated-gate field effect transistor | — | 1997-10-28 |
| 5679588 | Method for fabricating P-wells and N-wells having optimized field and active regions | Jeong Yeol Choi | 1997-10-21 |
| 5675165 | Stable SRAM cell using low backgate biased threshold voltage select transistors | — | 1997-10-07 |
| 5654213 | Method for fabricating a CMOS device | Jeong Yeol Choi, Chung-Jen Chien, Chung Chyung Han | 1997-08-05 |
| 5652456 | Semiconductor structure containing multiple optimized well regions | — | 1997-07-29 |
| 5644155 | Structure and fabrication of high capacitance insulated-gate field effect transistor | — | 1997-07-01 |
| 5643809 | Method for making high speed poly-emitter bipolar transistor | — | 1997-07-01 |
| 5644459 | Bipolarity electrostatic discharge protection device and method for making same | — | 1997-07-01 |
| 5574305 | Walled-emitter transistor | Kyle Terrill | 1996-11-12 |
| 5572460 | Static random-access memory cell with capacitive coupling to reduce sensitivity to radiation | — | 1996-11-05 |
| 5541433 | High speed poly-emitter bipolar transistor | — | 1996-07-30 |
| 5514613 | Parallel manufacturing of semiconductor devices and the resulting structure | Joseph F. Santadrea, Ji Min Lee, Alan H. Huggins | 1996-05-07 |
| 5510744 | Control circuit for reducing ground and power bounce from an output driver circuit | — | 1996-04-23 |
| 5479039 | MOS electrostatic discharge protection device and structure | — | 1995-12-26 |
| 5470766 | Efficient method for fabricating optimal BiCMOS N-wells for bipolar and field effect transistors | — | 1995-11-28 |
| 5471094 | Self-aligned via structure | — | 1995-11-28 |
| 5401997 | ESD protection for poly resistor on oxide | — | 1995-03-28 |
| 5393677 | Method of optimizing wells for PMOS and bipolar to yield an improved BICMOS process | Kyle Terrill, Jeong Yeol Choi | 1995-02-28 |
| 5310700 | Conductor capacitance reduction in integrated circuits | Jimmy Lee, Daniel Liao, Joe F. Santandrea | 1994-05-10 |
| 5284800 | Method for preventing the exposure of borophosphosilicate glass to the ambient and stopping phosphorus ions from infiltrating silicon in a semiconductor process | Daniel Liao, Jowei Dun | 1994-02-08 |
| 5258317 | Method for using a field implant mask to correct low doping levels at the outside edges of the base in a walled-emitter transistor structure | Kyle Terrill | 1993-11-02 |
| 5250854 | Bitline pull-up circuit operable in a low-resistance test mode | — | 1993-10-05 |
| 5182475 | ECL to CMOS voltage translator with bipolar transistor | — | 1993-01-26 |
| 5173627 | Circuit for outputting a data signal following an output enable command signal | — | 1992-12-22 |
| 5128731 | Static random access memory cell using a P/N-MOS transistors | Fu-Chieh Hsu, Jeong Yeol Choi, Jeng-Jiun Yang | 1992-07-07 |