Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7853420 | Performing temporal checking | Parag Birmiwal, Sundeep Chadha, Johannes Koesters | 2010-12-14 |
| 7720667 | Method and system for estimating power consumption of integrated circuitry | Rajat Chaudhry, Daniel Stasiak, Todd Swanson | 2010-05-18 |
| 7711875 | High speed on-chip serial link apparatus | Ingemar Holm, Ralph C. Koester, Mack W. Riley | 2010-05-04 |
| 7512925 | System and method for reducing test time for loading and executing an architecture verification program for a SoC | Parag Birmiwal, Mack W. Riley, Devi Shanmugam, Polisetty V. N. Srinivas | 2009-03-31 |
| 7509606 | Method for optimizing power in a very large scale integration (VLSI) design by detecting clock gating opportunities | Rajat Chaudhry, Daniel Stasiak, Todd Swanson | 2009-03-24 |
| 7478304 | Apparatus for accelerating through-the-pins LBIST simulation | Christian Habermann, Naoki Kiryu, Joachim Kneisel, Johannes Koesters | 2009-01-13 |
| 7464354 | Method and apparatus for performing temporal checking | Parag Birmiwal, Sundeep Chadha, Johannes Koesters | 2008-12-09 |
| 7430624 | High speed on-chip serial link apparatus and method | Ingemar Holm, Ralph C. Koester, Mack W. Riley | 2008-09-30 |
| 7386775 | Scan verification for a scan-chain device under test | Parag Birmiwal, Klaus Heinzelmann, Johannes Koesters | 2008-06-10 |
| 7350124 | Method and apparatus for accelerating through-the pins LBIST simulation | Christian Habermann, Naoki Kiryu, Joachim Kneisel, Johannes Koesters | 2008-03-25 |
| 7305636 | Method and system for formal unidirectional bus verification using synthesizing constrained drivers | Jason R. Baumgartner, Joachim Kneisel, Johannes Koesters | 2007-12-04 |