Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7055003 | Data cache scrub mechanism for large L2/L3 data cache structures | Guy L. Guthrie, Harmony L. Helterhoff, Kevin F. Reick | 2006-05-30 |
| 7055002 | Integrated purge store mechanism to flush L2/L3 cache structure for improved reliabity and serviceability | Guy L. Guthrie, Kevin F. Reick, Derek E. Williams | 2006-05-30 |
| 7047320 | Data processing system providing hardware acceleration of input/output (I/O) communication | Ravi Kumar Arimilli, Guy L. Guthrie, William J. Starke | 2006-05-16 |
| 7039832 | Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems | Ravi Kumar Arimilli, Guy L. Guthrie, William J. Starke | 2006-05-02 |
| 6996679 | Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members | Guy L. Guthrie, William J. Starke | 2006-02-07 |
| 6983347 | Dynamically managing saved processor soft states | Ravi Kumar Arimilli, Guy L. Guthrie, William J. Starke | 2006-01-03 |
| 6981083 | Processor virtualization mechanism via an enhanced restoration of hard architected states | Ravi Kumar Arimilli, Guy L. Guthrie, William J. Starke | 2005-12-27 |
| 6976148 | Acceleration of input/output (I/O) communication through improved address translation | Ravi Kumar Arimilli, Guy L. Guthrie, William J. Starke | 2005-12-13 |
| 6950892 | Method and system for managing distributed arbitration for multicycle data transfer requests | Robert H. Bell, Jr. | 2005-09-27 |
| 6748501 | Microprocessor reservation mechanism for a hashed address system | Ravi Kumar Arimilli, Guy L. Guthrie, Derek E. Williams | 2004-06-08 |
| 6606666 | Method and system for controlling information flow between a producer and a buffer in a high frequency digital system | Robert H. Bell, Jr., Leo James Clark, William J. Starke | 2003-08-12 |
| 6604145 | Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer and a shared data path | Robert H. Bell, Jr., Leo James Clark, William J. Starke | 2003-08-05 |
| 6601105 | Method and system for controlling information flow between a producer and multiple buffers in a high frequency digital system | Robert H. Bell, Jr., Leo James Clark, William J. Starke | 2003-07-29 |
| 6598086 | Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer | Robert H. Bell, Jr., Leo James Clark, William J. Starke | 2003-07-22 |
| 6499123 | Method and apparatus for debugging an integrated circuit | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 2002-12-24 |
| 6490653 | Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system | Bruce Joseph Ronchetti, David Shippy, Larry Edward Thatcher | 2002-12-03 |
| 6477637 | Method and apparatus for transporting store requests between functional units within a processor | Ravi Kumar Arimilli, Guy L. Guthrie | 2002-11-05 |
| 6212629 | Method and apparatus for executing string instructions | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 2001-04-03 |
| 5881265 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1999-03-09 |
| 5835946 | High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations | Michael S. Allen, Brad B. Beavers, Jose M. Nunez, David W. Todd, Jen-Tian Yen | 1998-11-10 |
| 5781753 | Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1998-07-14 |
| 5768575 | Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1998-06-16 |
| 5682492 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1997-10-28 |
| 5442757 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1995-08-15 |
| 5226126 | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1993-07-06 |