Issued Patents All Time
Showing 51–75 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7035958 | Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Thomas Andrew Sartorius, Barry Joe Wolford | 2006-04-25 |
| 6993619 | Single request data transfer regardless of size and alignment | Victor Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Thomas Andrew Sartorius, Barry Joe Wolford | 2006-01-31 |
| 6985972 | Dynamic cache coherency snooper presence with variable snoop latency | James Norris Dieffenderfer, Bernard C. Drerup, Jaya Prakash Subramaniam Ganasan, Thomas Andrew Sartorius, Thomas Philip Speier +1 more | 2006-01-10 |
| 6976132 | Reducing latency of a snoop tenure | James Norris Dieffenderfer, Bernard C. Drerup, Jaya Prakash Subramaniam Ganasan, Thomas Andrew Sartorius, Thomas Philip Speier +1 more | 2005-12-13 |
| 6973520 | System and method for providing improved bus utilization via target directed completion | Bernard C. Drerup, Jaya Prakash Subramaniam Ganasan, Richard Nicholas Iachetta, Jr., Barry Joe Wolford | 2005-12-06 |
| 6970816 | Method and system for efficiently generating parameterized bus transactions | Paul David Bryan, Peter Dean LaFauci, William Lee, Rhonda Gurganious Mitchell, Timothy P. Oke | 2005-11-29 |
| 6970962 | Transfer request pipeline throttling | James Norris Dieffenderfer, Bernard C. Drerup, Jaya Prakash Subramaniam Ganasan, Thomas Andrew Sartorius, Thomas Philip Speier +1 more | 2005-11-29 |
| 6907502 | Method for moving snoop pushes to the front of a request queue | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Jaya Prakash Subramaniam Ganasan, Thomas Andrew Sartorius +2 more | 2005-06-14 |
| 6857029 | Scalable on-chip bus performance monitoring synchronization mechanism and method of use | Jaya Prakash Subramaniam Ganasan, Adger Harvin, Perry Willmann Remaklus, Jr. | 2005-02-15 |
| 6834378 | System on a chip bus with automatic pipeline stage insertion for timing closure | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Thomas Andrew Sartorius, Barry Joe Wolford | 2004-12-21 |
| 6826656 | Reducing power in a snooping cache based multiprocessor environment | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Thomas Andrew Sartorius, Barry Joe Wolford | 2004-11-30 |
| 6823411 | N-way psuedo cross-bar having an arbitration feature using discrete processor local busses | Barry Joe Wolford | 2004-11-23 |
| 6807608 | Multiprocessor environment supporting variable-sized coherency transactions | Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard C. Drerup, Thomas Andrew Sartorius, Barry Joe Wolford | 2004-10-19 |
| 6772254 | Multi-master computer system with overlapped read and write operations and scalable address pipelining | Jason Michael Hopp, Peter Dean LaFauci, Dennis Charles Wilkerson | 2004-08-03 |
| 6633994 | Method and system for optimizing data transfers between devices interconnected by buses operating at different clocking speeds | Jason Michael Hopp, Rhonda Gurganious Mitchell, Dennis Charles Wilkerson | 2003-10-14 |
| 6587905 | Dynamic data bus allocation | Anthony Correale, Jr., Peter Dean LaFauci, Dennis Charles Wilkerson | 2003-07-01 |
| 6513089 | Dual burst latency timers for overlapped read and write data transfers | Peter Dean LaFauci, Dennis Charles Wilkerson | 2003-01-28 |
| 6504854 | Multiple frequency communications | Mark Michael Schaffer, Thomas Andrew Sartorius | 2003-01-07 |
| 6430641 | Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system | Peter Dean LaFauci, Dennis Charles Wilkerson | 2002-08-06 |
| 6055584 | Processor local bus posted DMA FlyBy burst transfers | Jeffrey Todd Bridges, Edward Hammond Green, III, David Otero, Mark Michael Schaffer, Dennis Charles Wilkerson | 2000-04-25 |
| 6047336 | Speculative direct memory access transfer between slave devices and memory | Edward Hammond Green, III, Mark Michael Schaffer, Dennis Charles Wilkerson | 2000-04-04 |
| 6032238 | Overlapped DMA line transfers | Edward Hammond Green, III, Mark Michael Schaffer, Dennis Charles Wilkerson | 2000-02-29 |
| 5642489 | Bridge between two buses of a computer system with a direct memory access controller with accessible registers to support power management | Patrick M. Bland, Dennis Moeller, Lance M. Venarchick | 1997-06-24 |
| 5623697 | Bridge between two buses of a computer system with a direct memory access controller having a high address extension and a high count extension | Patrick M. Bland, Daniel R. Cronin, III, Dennis Moeller, Lance M. Venarchick | 1997-04-22 |
| 5621902 | Computer system having a bridge between two buses with a direct memory access controller and an alternative memory access controller | Moises Cases, Lance M. Venarchick | 1997-04-15 |