Issued Patents All Time
Showing 26–50 of 106 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8893148 | Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, William E. Speight | 2014-11-18 |
| 8843705 | Read and write aware cache with a read portion and a write portion of a tag and status array | Jian Li, William E. Speight, Lixin Zhang | 2014-09-23 |
| 8811378 | Dual network types solution for computer interconnects | Alan F. Benner, Eugen Schenfeld, Craig Brian Stunkel, Peter Walker | 2014-08-19 |
| 8756608 | Method and system for performance isolation in virtualized environments | Elmootazbellah Nabil Elnozahy, William E. Speight, Lixin Zhang | 2014-06-17 |
| 8543769 | Fine grained cache allocation | William E. Speight, Lixin Zhang | 2013-09-24 |
| 8484307 | Host fabric interface (HFI) to perform global shared memory (GSM) operations | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, William J. Starke +1 more | 2013-07-09 |
| 8452850 | Method, apparatus and computer program product to crawl a web site | Elizabeth A. Brodsky, Elmootazbellah Nabil Elnozahy | 2013-05-28 |
| 8417913 | Superpage coalescing which supports read/write access to a new virtual superpage mapping during copying of physical pages | Elmootazbellah Nabil Elnozahy, James L. Peterson, Hazim Shafi | 2013-04-09 |
| 8370517 | Conserving energy in a data processing network | Patrick J. Bohrer, Bishop Brock, Elmootazbellah Nabil Elnozahy, Freeman Leigh Rawson, III | 2013-02-05 |
| 8312464 | Hardware based dynamic load balancing of message passing interface tasks by modifying tasks | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, William E. Speight | 2012-11-13 |
| 8275947 | Mechanism to prevent illegal access to task address space by unauthorized tasks | Lakshminarayana B. Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2012-09-25 |
| 8271729 | Read and write aware cache storing cache lines in a read-often portion and a write-often portion | Jian Li, William E. Speight, Lixin Zhang | 2012-09-18 |
| 8255591 | Method and system for managing cache injection in a multiprocessor system | Patrick J. Bohrer, Ahmed Gheith, Peter Hochschild, Hazim Shafi, Balaram Sinharoy | 2012-08-28 |
| 8255913 | Notification to task of completion of GSM operations by initiator node | Lakshminarayana B. Arimilli, Robert S. Blackmore, Gheorghe C. Cascaval | 2012-08-28 |
| 8239879 | Notification by task of completion of GSM operations at target node | Lakshminarayana B. Arimilli, Robert S. Blackmore, Gheorghe C. Cascaval | 2012-08-07 |
| 8234652 | Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, William E. Speight | 2012-07-31 |
| 8230422 | Assist thread for injecting cache memory in a microprocessor | Patrick J. Bohrer, Orran Krieger, Michael Rosenfield, Hazim Shafi, Balaram Sinharoy +1 more | 2012-07-24 |
| 8214604 | Mechanisms to order global shared memory operations | Lakshminarayana B. Armilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2012-07-03 |
| 8200910 | Generating and issuing global shared memory operations via a send FIFO | Lakshminarayana B. Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2012-06-12 |
| 8194638 | Dual network types solution for computer interconnects | Alan F. Benner, Eugen Schenfeld, Craig Brian Stunkel, Peter Walker | 2012-06-05 |
| 8185896 | Method for data processing using a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Edward J. Seminaro, William E. Speight | 2012-05-22 |
| 8146094 | Guaranteeing delivery of multi-packet GSM messages | Lakshminarayana B. Arimilli, Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2012-03-27 |
| 8140759 | Specifying an access hint for prefetching partial cache block data in a cache hierarchy | Bradly G. Frey, Guy L. Guthrie, Cathy May, Balaram Sinharoy, William J. Starke +1 more | 2012-03-20 |
| 8140731 | System for data processing using a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Edward J. Seminaro, William E. Speight | 2012-03-20 |
| 8127300 | Hardware based dynamic load balancing of message passing interface tasks | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, William E. Speight | 2012-02-28 |