Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7049947 | System and method for monitoring the operational condition of a motor vehicle | Sanjeev Nath | 2006-05-23 |
| 7013366 | Parallel search technique for store operations | James David Dundas, Mukesh Patel | 2006-03-14 |
| 6678807 | System and method for multiple store buffer forwarding in a system with a restrictive memory model | Bryan Boatright, Larry Edward Thatcher | 2004-01-13 |
| 6611900 | System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model | Bryan Boatright, Larry Edward Thatcher | 2003-08-26 |
| 6463511 | System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model | Bryan Boatright, Larry Edward Thatcher | 2002-10-08 |
| 6321303 | Dynamically modifying queued transactions in a cache memory system | Thomas Hoy, Belliappa Kuttanna, Michael D. Snyder | 2001-11-20 |
| 6311254 | Multiple store miss handling in a cache memory memory system | Belliappa Kuttanna, Michael D. Snyder | 2001-10-30 |
| 6269427 | Multiple load miss handling in a cache memory system | Belliappa Kuttanna, Michael D. Snyder | 2001-07-31 |
| 6119203 | Mechanism for sharing data cache resources between data prefetch operations and normal load/store operations in a data processing system | Michael D. Snyder | 2000-09-12 |
| 5974505 | Method and system for reducing power consumption of a non-blocking cache within a data processing system | Belliappa Kuttanna | 1999-10-26 |
| 5897654 | Method and system for efficiently fetching from cache during a cache fill operation | Lee Evan Eisen, Belliappa Kuttanna, Soummya Mallick | 1999-04-27 |
| 5895486 | Method and system for selectively invalidating cache lines during multiple word store operations for memory coherence | — | 1999-04-20 |
| 5873123 | Processor and method for translating a nonphysical address into a physical address utilizing a selectively nonsequential search of page table entries | Gunendran Thuraisingham, Belliappa Kuttanna | 1999-02-16 |
| 5860107 | Processor and method for store gathering through merged store operations | — | 1999-01-12 |
| 5809526 | Data processing system and method for selective invalidation of outdated lines in a second level memory in response to a memory request initiated by a store operation | — | 1998-09-15 |
| 5802572 | Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache | Soummya Mallick | 1998-09-01 |
| 5802340 | Method and system of executing speculative store instructions in a parallel processing computer system | Soummya Mallick | 1998-09-01 |
| 5802556 | Method and apparatus for correcting misaligned instruction data | Soummya Mallick | 1998-09-01 |
| 5787479 | Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation | Romesh Mangho Jessani, Belliappa Kuttanna, Soummya Mallick | 1998-07-28 |
| 5765191 | Method for implementing a four-way least recently used (LRU) mechanism in high-performance | Albert J. Loper, Soummya Mallick, Michael Putrino | 1998-06-09 |
| 5764940 | Processor and method for executing a branch instruction and an associated target instruction utilizing a single instruction fetch | Soummya Mallick, Romesh Mangho Jessani | 1998-06-09 |
| 5758117 | Method and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processor | Soummya Mallick | 1998-05-26 |
| 5737749 | Method and system for dynamically sharing cache capacity in a microprocessor | Romesh Mangho Jessani, Belliappa Kuttana | 1998-04-07 |
| 5737751 | Cache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing system | Sung Ho Park, Romesh Mangho Jessani, Belliappa Kuttanna | 1998-04-07 |
| 5721867 | Method and apparatus for executing single beat write store instructions during a cache store linefill operation | Belliappa Kuttanna, Sung Ho Park | 1998-02-24 |