Issued Patents All Time
Showing 51–67 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8677180 | Switch failover control in a multiprocessor computer system | Gerd Bayer, David F. Craddock, Thomas A. Gregg, Michael Jung, Andreas Kohler +2 more | 2014-03-18 |
| 8650335 | Measurement facility for adapter functions | Frank W. Brice, Jr., David F. Craddock, Beth A. Glendening, Thomas A. Gregg, Eric N. Lais +1 more | 2014-02-11 |
| 8615645 | Controlling the selectively setting of operational parameters for an adapter | David F. Craddock, Mark S. Farrell, Beth A. Glendening, Thomas A. Gregg, Dan F. Greiner +1 more | 2013-12-24 |
| 8582778 | Integrated key server | Edward W. Chencinski, James R. Coon, John C. Dayka, Steven G. Glassen, Richard J. Gusefski +5 more | 2013-11-12 |
| 8510599 | Managing processing associated with hardware events | Anthony F. Coneski, David F. Craddock, Charles W. Gainey, Jr., Beth A. Glendening, Thomas A. Gregg +1 more | 2013-08-13 |
| 8447949 | Detection of zero address events in address formation | Robert M. Abrams, Mark S. Farrell, Dan F. Greiner, Christian Jacobi, James H. Mulder +2 more | 2013-05-21 |
| 8364912 | Use of test protection instruction in computing environments that support pageable guests | Mark S. Farrell, Lisa C. Heller, Damian L. Osisek | 2013-01-29 |
| 8311051 | Use of hardware to manage dependencies between groups of network data packets | Douglas G. Balazich, Carl A. Bender, Douglas J. Joseph | 2012-11-13 |
| 8176280 | Use of test protection instruction in computing environments that support pageable guests | Mark S. Farrell, Lisa C. Heller, Damian L. Osisek | 2012-05-08 |
| 8176254 | Specifying an access hint for prefetching limited use data in a cache hierarchy | Bradly G. Frey, Guy L. Guthrie, Cathy May, Balaram Sinharoy | 2012-05-08 |
| 8140759 | Specifying an access hint for prefetching partial cache block data in a cache hierarchy | Bradly G. Frey, Guy L. Guthrie, Cathy May, Ramakrishnan Rajamony, Balaram Sinharoy +1 more | 2012-03-20 |
| 7724757 | Use of hardware to manage dependencies between groups of network data packets | Douglas G. Balazich, Carl A. Bender, Douglas J. Joseph | 2010-05-25 |
| 7408945 | Use of hardware to manage dependencies between groups of network data packets | Douglas G. Balazich, Carl A. Bender, Douglas J. Joseph | 2008-08-05 |
| 7099997 | Read-modify-write avoidance using a boundary word storage mechanism | Douglas G. Balazich, Douglas J. Joseph, Carl A. Bender | 2006-08-29 |
| 5901326 | Memory bus address snooper logic for determining memory activity without performing memory accesses | Kevin J. Gildea, Peter Hochschild | 1999-05-04 |
| 5450602 | Two stage register for capturing asynchronous events and subsequently providing them to a processor without loss or duplication of the captured events | — | 1995-09-12 |
| 5363484 | Multiple computer system with combiner/memory interconnection system employing separate direct access link for transferring information packets | Christine M. Desnoyers, Derrick LeRoy Garmire, Sheryl M. Genco, Donald G. Grice, William R. Milani +5 more | 1994-11-08 |