Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6480897 | Optimistic transmission flow control including receiver data discards upon inadequate buffering condition | Douglas J. Joseph, Francis A. Kampf, Alan F. Benner | 2002-11-12 |
| 6338091 | System for optimistic transmission flow control including receiver data discards upon inadequate buffering condition | Douglas J. Joseph, Francis A. Kampf, Alan F. Benner | 2002-01-08 |
| 6337852 | Flow control system using control information of a message for initiating retransmission of data portion when buffer is available | Douglas J. Joseph, Francis A. Kampf, Alan F. Benner | 2002-01-08 |
| 6185693 | Synchronous interface for transmitting data in a system of massively parallel processors | Derrick LeRoy Garmire, Robert S. Capowski, Daniel F. Casper, Frank D. Ferraiolo, Marten J. Halma +1 more | 2001-02-06 |
| 6105071 | Source and destination initiated interrupt system for message arrival notification | Douglas J. Joseph, Francis A. Kampf | 2000-08-15 |
| 6098104 | Source and destination initiated interrupts for message arrival notification, and related data structures | Douglas J. Joseph, Francis A. Kampf | 2000-08-01 |
| 6098105 | Source and destination initiated interrupt method for message arrival notification | Douglas J. Joseph, Francis A. Kampf | 2000-08-01 |
| 5968189 | System of reporting errors by a hardware element of a distributed computer system | Derrick LeRoy Garmire, Antoinette Elaine Herrmann, Francis A. Kampf, Robert Frederick Stucke | 1999-10-19 |
| 5923840 | Method of reporting errors by a hardware element of a distributed computer system | Derrick LeRoy Garmire, Antoinette Elaine Herrmann, Francis A. Kampf, Robert Frederick Stucke | 1999-07-13 |
| 5694612 | Self-timed interface for a network of computer processors interconnected in parallel | Derrick LeRoy Garmire, Robert S. Capowski, Daniel F. Casper, Frank D. Ferraiolo, Marten J. Halma +1 more | 1997-12-02 |
| 5594918 | Parallel computer system providing multi-ported intelligent memory | Billy J. Knowles, Clive A. Collins, Donald G. Grice, David B. Rolfe | 1997-01-14 |
| 5555528 | Dynamic random access memory persistent page implemented as processor register sets | Clive A. Collins, Billy J. Knowles, David B. Rolfe, Dale E. Pontius | 1996-09-10 |
| 5519664 | Dynamic random access memory persistent page implemented as processor register sets | Clive A. Collins, Billy J. Knowles, David B. Rolfe, Dale E. Pontius | 1996-05-21 |
| 5508968 | Dynamic random access memory persistent page implemented as processor register sets | Clive A. Collins, Billy J. Knowles, David B. Rolfe, Dale E. Pontius | 1996-04-16 |
| 5363484 | Multiple computer system with combiner/memory interconnection system employing separate direct access link for transferring information packets | Derrick LeRoy Garmire, Sheryl M. Genco, Donald G. Grice, William R. Milani, Michael Patrick Muhlada +5 more | 1994-11-08 |