Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7194714 | Method of reducing instantaneous current draw and an integrated circuit made thereby | Norman J. Rohrer | 2007-03-20 |
| 7127560 | Method of dynamically controlling cache size | Erwin B. Cohen, Thomas E. Cook, Ian R. Govett, Stephen V. Kosonocky, Peter A. Sandon +1 more | 2006-10-24 |
| 7127689 | Method for preventing circuit failures due to gate oxide leakage | Thomas G. Mitchell, Norman J. Rohrer, Ronald D. Rose | 2006-10-24 |
| 7057180 | Detector for alpha particle or cosmic ray | John A. Fifield, William A. Klaasen, Stephen V. Kosonocky, Randy W. Mann, Jeffery H. Oppold +1 more | 2006-06-06 |
| 6954916 | Methodology for fixing Qcrit at design timing impact | Kerry Bernstein, Philip G. Emma, Leendert M. Huisman, Norman J. Rohrer | 2005-10-11 |
| 6891419 | Methods and apparatus for employing feedback body control in cross-coupled inverters | Stephen V. Kosonocky, Randy W. Mann, Norman J. Rohrer | 2005-05-10 |
| 6794901 | Apparatus for reducing soft errors in dynamic circuits | Kerry Bernstein, Philip G. Emma, John A. Fifield, Norman J. Rohrer, Peter A. Sandon | 2004-09-21 |
| 6201425 | Method and apparatus for reducing charge sharing and the bipolar effect in stacked SOI circuits | Norman J. Rohrer | 2001-03-13 |
| 5872462 | Programmable logic array and method for its design using a three step approach | Gary S. Ditlow | 1999-02-16 |
| 5867038 | Self-timed low power ratio-logic system having an input sensing circuit | Norman J. Rohrer, Timothy Jon Sulzbach | 1999-02-02 |
| 5811988 | PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output | Gary S. Ditlow | 1998-09-22 |
| 5719505 | Reduced power PLA | Gary S. Ditlow | 1998-02-17 |
| 5717344 | PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output | Gary S. Ditlow | 1998-02-10 |
| 5712790 | Method of power reduction in pla's | Gary S. Ditlow | 1998-01-27 |
| 5644744 | Superscaler instruction pipeline having boundary identification logic for variable length instructions | Stephen W. Mahin, Stephen M. Conor, Stephen J. Ciavaglia, Lyman Moulton, Stephen E. Rich | 1997-07-01 |
| 5640526 | Superscaler instruction pipeline having boundary indentification logic for variable length instructions | Stephen W. Mahin, Stephen M. Conor, Stephen J. Ciavaglia, Lyman Moulton, Stephen E. Rich | 1997-06-17 |
| 5625787 | Superscalar instruction pipeline using alignment logic responsive to boundary identification logic for aligning and appending variable length instructions to instructions stored in cache | Stephen W. Mahin, Stephen M. Conor, Stephen J. Ciavaglia, Lyman Moulton, Stephen E. Rich | 1997-04-29 |
| 5572150 | Low power pre-discharged ratio logic | Norman J. Rohrer | 1996-11-05 |