Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6960523 | Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device | Michael Maldei, Prakash Dev, David M. Dobuzinsky, Johnathan E. Faltermeier, Thomas Rupp +3 more | 2005-11-01 |
| 6197267 | Catalytic reactor | — | 2001-03-06 |
| 6193832 | Method of making dielectric catalyst structures | — | 2001-02-27 |
| 6177337 | Method of reducing metal voids in semiconductor device interconnection | — | 2001-01-23 |
| 6177286 | Reducing metal voids during BEOL metallization | Dureseti Chidambarrao | 2001-01-23 |
| 6130182 | Dielectric catalyst structures | — | 2000-10-10 |
| 6066566 | High selectivity collar oxide etch processes | Matthew Sendelbach, Ting Wang | 2000-05-23 |