Issued Patents All Time
Showing 51–75 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9335993 | Convert from zoned format to decimal floating point format | Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Eric M. Schwarz, Timothy J. Slegel | 2016-05-10 |
| 9329861 | Convert to zoned format from decimal floating point format | Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Eric M. Schwarz, Timothy J. Slegel | 2016-05-03 |
| 9280448 | Controlling operation of a run-time instrumentation facility from a lesser-privileged state | Mark S. Farrell, Charles W. Gainey, Jr., Chung-Lung K. Shum, Timothy J. Slegel, Brian L. Smith +1 more | 2016-03-08 |
| 9280346 | Run-time instrumentation reporting | Mark S. Farrell, Charles W. Gainey, Jr., Chung-Lung K. Shum, Brian L. Smith | 2016-03-08 |
| 9268543 | Efficient code cache management in presence of infrequently used complied code fragments | Patrick R. Doyle, Marius Pirvu, Kevin A. Stoodley, Vijay Sundaresan | 2016-02-23 |
| 9229725 | Safe conditional-load and conditional-store operations | Visda Vokhshoori | 2016-01-05 |
| 9158566 | Page mapped spatially aware emulation of computer instruction set | Theodore J. Bohizic, Reid T. Copeland, Ali I. Sheikh | 2015-10-13 |
| 9158660 | Controlling operation of a run-time instrumentation facility | Mark S. Farrell, Charles W. Gainey, Jr., Chung-Lung K. Shum, Timothy J. Slegel, Brian L. Smith +1 more | 2015-10-13 |
| 9146739 | Branch prediction preloading | James J. Bonanno, Brian R. Prasky, Joran S. C. Siu, Timothy J. Slegel, Alexander Vasilevskiy | 2015-09-29 |
| 9146740 | Branch prediction preloading | James J. Bonanno, Brian R. Prasky, Joran S. C. Siu, Timothy J. Slegel, Alexander Vasilevskiy | 2015-09-29 |
| 9052889 | Load pair disjoint facility and instruction therefor | Christian Jacobi, Timothy J. Slegel, Charles F. Webb | 2015-06-09 |
| 8949106 | Just in time compiler in spatially aware emulation of a guest computer instruction set | Theodore J. Bohizic, Reid T. Copeland, Ali I. Sheikh | 2015-02-03 |
| 8914619 | High-word facility for extending the number of general purpose registers available to instructions | Dan F. Greiner, Timothy J. Slegel | 2014-12-16 |
| 8887003 | Transaction diagnostic block | Dan F. Greiner, Christian Jacobi, Timothy J. Slegel | 2014-11-11 |
| 8880959 | Transaction diagnostic block | Dan F. Greiner, Christian Jacobi, Timothy J. Slegel | 2014-11-04 |
| 8850166 | Load pair disjoint facility and instruction therefore | Christian Jacobi, Timothy J. Slegel, Charles F. Webb | 2014-09-30 |
| 8819647 | Performance improvements for nested virtual machines | Ali I. Sheikh | 2014-08-26 |
| 8776033 | Batch dispatch of java native interface calls | Andrew R. Low, Kishor V. Patil, Gavin Rolleston, Ivan King Yu Sham, Karl M. Taylor | 2014-07-08 |
| 8768683 | Self initialized host cell spatially aware emulation of a computer instruction set | Theodore J. Bohizic, Reid T. Copeland, Ali I. Sheikh | 2014-07-01 |
| 8689172 | Mining sequential patterns in weighted directed graphs | Jose N. Amaral, Adam Paul Jocksch | 2014-04-01 |
| 8683423 | Mining sequential patterns in weighted directed graphs | Jose N. Amaral, Adam Paul Jocksch | 2014-03-25 |
| 8639492 | Accelerated execution for emulated environments | Francis Bogsanyl, Graeme Johnson, Andrew R. Low, Ali I. Sheikh | 2014-01-28 |
| 8490073 | Controlling tracing within compiled code | — | 2013-07-16 |
| 8448157 | Eliminating redundant operations for common properties using shared real registers | Kishor V. Patil, Joran S. C. Siu, Mark Graham Stoodley, Vijay Sundaresan | 2013-05-21 |
| 8447583 | Self initialized host cell spatially aware emulation of a computer instruction set | Theodore J. Bohizic, Reid T. Copeland, Ali I. Sheikh | 2013-05-21 |