Issued Patents All Time
Showing 76–88 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8438340 | Executing atomic store disjoint instructions | Theodore J. Bohizic, Reid T. Copeland | 2013-05-07 |
| 8428930 | Page mapped spatially aware emulation of a computer instruction set | Theodore J. Bohizic, Reid T. Copeland, Ali I. Sheikh | 2013-04-23 |
| 8387031 | Providing code improvements for nested virtual machines | Derek B. Inglis, Ali I. Sheikh, Kevin A. Stoodley | 2013-02-26 |
| 8301434 | Host cell spatially aware emulation of a guest wild branch | Theodore J. Bohizic, Reid T. Copeland, Ali I. Sheikh | 2012-10-30 |
| 8250557 | Configuring a dependency graph for dynamic by-pass instruction scheduling | Alexander Vasilevskiy | 2012-08-21 |
| 8042100 | Methods, systems, and computer products for evaluating robustness of a list scheduling framework | Joran S. C. Siu, Alexander Vasilevskiy | 2011-10-18 |
| 7937552 | Cache line reservations | Daryl James Maier, Vijay Sundaresan | 2011-05-03 |
| 7930686 | Defining memory indifferent trace handles | Ali Sheikh | 2011-04-19 |
| 7908596 | Automatic inspection of compiled code | Alexander Vasilevskiy | 2011-03-15 |
| 7899856 | Hysteresis for mixed representation of Java BigDecimal objects | Alexander S. Ross, Levon Stepanian | 2011-03-01 |
| 7770161 | Post-register allocation profile directed instruction scheduling | Alexander Vasilevskiy | 2010-08-03 |
| 7617493 | Defining memory indifferent trace handles | Ali I. Sheikh | 2009-11-10 |
| 7392516 | Method and system for configuring a dependency graph for dynamic by-pass instruction scheduling | Alexander Vasilevskiy | 2008-06-24 |