Issued Patents All Time
Showing 76–100 of 130 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7840703 | System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture | Ravi Kumar Arimilli, Ramakrishnan Rajamony | 2010-11-23 |
| 7827428 | System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture | Ravi Kumar Arimilli, Bernard C. Drerup, Jody B. Joyner, Jerry Don Lewis | 2010-11-02 |
| 7822889 | Direct/indirect transmission of information using a multi-tiered full-graph interconnect architecture | Ravi Kumar Arimilli, Ramakrishnan Rajamony | 2010-10-26 |
| 7809970 | System and method for providing a high-speed message passing interface for barrier operations in a multi-tiered full-graph interconnect architecture | Ravi Kumar Arimilli, Ramakrishnan Rajamony | 2010-10-05 |
| 7797588 | Mechanism to provide software guaranteed reliability for GSM operations | Robert S. Blackmore, Chulho Kim, Hanhong Xue | 2010-09-14 |
| 7793158 | Providing reliability of communication between supernodes of a multi-tiered full-graph interconnect architecture | Ravi Kumar Arimilli, Ramakrishnan Rajamony | 2010-09-07 |
| 7779148 | Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips | Ravi Kumar Arimilli, Bernard C. Drerup, Jody B. Joyner, Jerry Don Lewis | 2010-08-17 |
| 7769891 | System and method for providing multiple redundant direct routes between supernodes of a multi-tiered full-graph interconnect architecture | Ravi Kumar Arimilli, Ramakrishnan Rajamony | 2010-08-03 |
| 7769892 | System and method for handling indirect routing of information between supernodes of a multi-tiered full-graph interconnect architecture | Ravi Kumar Arimilli, Ramakrishnan Rajamony | 2010-08-03 |
| 6633838 | Multi-state logic analyzer integral to a microprocessor | Michael Stephen Floyd, Larry Scott Leitner, Kevin F. Reick, Jennifer L. Vargus | 2003-10-14 |
| 6629209 | Cache coherency protocol permitting sharing of a locked data granule | Ravi Kumar Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6629214 | Extended cache coherency protocol with a persistent “lock acquired” state | Ravi Kumar Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6629212 | High speed lock acquisition mechanism with time parameterized cache coherency states | Ravi Kumar Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6625701 | Extended cache coherency protocol with a modified store instruction lock release indicator | Ravi Kumar Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2003-09-23 |
| 6581115 | Data processing system with configurable memory bus and scalability ports | Ravi Kumar Arimilli, Leo James Clark, James S. Fields, Jr. | 2003-06-17 |
| 6581139 | Set-associative cache memory having asymmetric latency among sets | Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields, Jr., Guy L. Guthrie | 2003-06-17 |
| 6553463 | Method and system for high speed access to a banked cache memory | Ravi Kumar Arimilli, James Stephen Fields, Jr., Sanjeev Ghai, Praveen S. Reddy | 2003-04-22 |
| 6549989 | Extended cache coherency protocol with a “lock released” state | Ravi Kumar Arimilli, John Steven Dodson, Guy L. Guthrie, William J. Starke | 2003-04-15 |
| 6535939 | Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations | Ravi Kumar Arimilli, Leo James Clark, James S. Fields, Jr. | 2003-03-18 |
| 6532521 | Mechanism for high performance transfer of speculative request data between levels of cache hierarchy | Ravi Kumar Arimilli, Leo James Clark, John Steven Dodson, Guy L. Guthrie, James Stephen Fields, Jr. | 2003-03-11 |
| 6510494 | Time based mechanism for cached speculative data deallocation | Ravi Kumar Arimilli, Leo James Clark, John Steven Dodson, Guy L. Guthrie, James Stephen Fields, Jr. | 2003-01-21 |
| 6505277 | Method for just-in-time delivery of load data by intervening caches | Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis | 2003-01-07 |
| 6496921 | Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions | Ravi Kumar Arimilli, Leo James Clark, John Steven Dodson, Guy L. Guthrie, James Stephen Fields, Jr. | 2002-12-17 |
| 6473833 | Integrated cache and directory structure for multi-level caches | Ravi Kumar Arimilli, Leo James Clark, James Stephen Fields, Jr. | 2002-10-29 |
| 6467030 | Method and apparatus for forwarding data in a hierarchial cache memory architecture | Ravi Kumar Arimilli, James Stephen Fields, Jr., Sanjeev Ghai, Praveen S. Reddy | 2002-10-15 |