Issued Patents All Time
Showing 26–50 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9977485 | Cache array with reduced power consumption | Paul A. Bunce, Diana M. Henderson, Jigar Vora | 2018-05-22 |
| 9971394 | Cache array with reduced power consumption | Paul A. Bunce, Diana M. Henderson, Jigar Vora | 2018-05-15 |
| 9966958 | Dynamic decode circuit with active glitch control | Paul A. Bunce, Yuen H. Chan, Antonio R. Pelella | 2018-05-08 |
| 9792967 | Managing semiconductor memory array leakage current | Paul A. Bunce, Yuen H. Chan, Silke Penth, David Edward Schmitt, Tobias Werner +1 more | 2017-10-17 |
| 9786339 | Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation | Paul A. Bunce, Yuen H. Chan, Silke Penth, David Edward Schmitt, Tobias Werner +1 more | 2017-10-10 |
| 9761289 | Managing semiconductor memory array leakage current | Paul A. Bunce, Yuen H. Chan, Silke Penth, David Edward Schmitt, Tobias Werner +1 more | 2017-09-12 |
| 9742408 | Dynamic decode circuit with active glitch control | Paul A. Bunce, Yuen H. Chan, Antonio R. Pelella | 2017-08-22 |
| 9583211 | Incorporating bit write capability with column interleave write enable and column redundancy steering | Paul A. Bunce, Russell Hayes, Brian James Yavoich | 2017-02-28 |
| 9550282 | Compact hydraulic torque wrench cartridge | — | 2017-01-24 |
| 9355692 | High frequency write through memory device | Paul A. Bunce, Yuen H. Chan, Diana M. Henderson, Jigar Vora | 2016-05-31 |
| 9281024 | Write/read priority blocking scheme using parallel static address decode path | Paul A. Bunce, Yuen H. Chan, Diana M. Henderson | 2016-03-08 |
| 9281025 | Write/read priority blocking scheme using parallel static address decode path | Paul A. Bunce, Yuen H. Chan, Diana M. Henderson | 2016-03-08 |
| 9070433 | SRAM supply voltage global bitline precharge pulse | Paul A. Bunce, Yuen H. Chan, Diana M. Henderson | 2015-06-30 |
| 8861284 | Increasing memory operating frequency | Paul A. Bunce, Diana M. Henderson, Jigar Vora | 2014-10-14 |
| 8599642 | Port enable signal generation for gating a memory array device output | Paul A. Bunce, Diana M. Henderson, Jigar Vora | 2013-12-03 |
| 8351278 | Jam latch for latching memory array output data | Paul A. Bunce, Diana M. Henderson, Jigar Vora | 2013-01-08 |
| 8345497 | Internal bypassing of memory array devices | Paul A. Bunce, Diana M. Henderson, Jigar Vora | 2013-01-01 |
| 8345490 | Split voltage level restore and evaluate clock signals for memory address decoding | Paul A. Bunce, Diana M. Henderson, Jigar Vora | 2013-01-01 |
| 8299833 | Programmable control clock circuit including scan mode | Paul A. Bunce, Yuen H. Chan, Richard Edward Serton | 2012-10-30 |
| 8102559 | System and method for controlling printing applications over variable layouts | Rickey M. Fullmer, Michael S. Lafranzo, Richard L. Lenski, Charles Novak | 2012-01-24 |
| 7926389 | Hydraulic torque wrench with central strain decoupled global hose connect swivel | — | 2011-04-19 |
| 7688650 | Write control method for a memory array configured with multiple memory subarrays | Paul A. Bunce, Donald W. Plass, Kenneth J. Reyer | 2010-03-30 |
| 7620594 | Systems and methods of managing prepayment | Stephen P. Traynor | 2009-11-17 |
| 7546765 | Scanning device and method for analyzing a road surface | Richard D. Janke, Mine Tasci, James C. Tebbe, Herbert R. Butterfield, Timothy D. Roberts +3 more | 2009-06-16 |
| 7471590 | Write control circuitry and method for a memory array configured with multiple memory subarrays | Paul A. Bunce, Donald W. Plass, Kenneth J. Reyer | 2008-12-30 |