Issued Patents All Time
Showing 51–75 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7299372 | Hierarchical management for multiprocessor system with real-time attributes | Jeffrey Douglas Brown, Michael Norman Day, Charles Ray Johns, James Allan Kahle, Michael Fan Wang | 2007-11-20 |
| 7279996 | Method of functionality testing for a ring oscillator | David William Boerstler, Eskinder Hailu, John Liberty | 2007-10-09 |
| 7233212 | Oscillator array with row and column control | David William Boerstler, Eskinder Hailu, John Liberty | 2007-06-19 |
| 7233998 | Computer architecture and software cells for broadband networks | Masakazu Suzuoki, Takeshi Yamazaki, Martin E. Hopkins, Charles Ray Johns, James Allan Kahle +2 more | 2007-06-19 |
| 7200688 | System and method asynchronous DMA command completion notification by accessing register via attached processing unit to determine progress of DMA command | Michael Norman Day, Charles Ray Johns, Peichum Peter Liu, Thuong Quang Truong, Takeshi Yamazaki | 2007-04-03 |
| 7197655 | Lowered PU power usage method and apparatus | Brian Flachs, John Liberty | 2007-03-27 |
| 7174410 | Method, apparatus and computer program product for write data transfer | Bernard C. Drerup, Wendel Glenn Voigt, Barry Joe Wolford | 2007-02-06 |
| 7120748 | Software-controlled cache set management | Michael Norman Day, Charles Johns, James Allan Kahle, David Shippy, Thuong Quang Truong +1 more | 2006-10-10 |
| 7114035 | Software-controlled cache set management with software-generated class identifiers | Michael Norman Day, Charles Ray Johns, James Allan Kahle, David Shippy, Thuong Quang Truong +1 more | 2006-09-26 |
| 7103748 | Memory management for real-time applications | Michael Norman Day, Charles Ray Johns, James Allan Kahle, David Shippy, Thuong Quang Truong | 2006-09-05 |
| 7093080 | Method and apparatus for coherent memory structure of heterogeneous processor systems | Michael Norman Day, Charles Ray Johns, James Allan Kahle, David Shippy, Thuong Quang Truong | 2006-08-15 |
| 7043579 | Ring-topology based multiprocessor data access bus | Sang Hoo Dhong, John Liberty, Peichun Peter Liu | 2006-05-09 |
| 6996233 | System and method for encrypting and verifying messages using three-phase encryption | Daniel Alan Brokenshire, David Craft, Mohammad Peyravian | 2006-02-07 |
| 6982954 | Communications bus with redundant signal paths and method for compensating for signal path errors in a communications bus | Sang Hoo Dhong | 2006-01-03 |
| 6983387 | Microprocessor chip simultaneous switching current reduction method and apparatus | David William Boerstler, Sang Hoo Dhong, Peichun Peter Liu | 2006-01-03 |
| 6981072 | Memory management in multiprocessor system | Michael Norman Day, Charles Ray Johns, James Allan Kahle, David Shippy, Thuong Quang Truong | 2005-12-27 |
| 6970982 | Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions | Erik R. Altman, Peter G. Capek, Michael K. Gschwind, James Allan Kahle, Ravi Nair +2 more | 2005-11-29 |
| 6941335 | Random carry-in for floating-point operations | Sang Hoo Dhong, Kevin John Nowka, Steven Douglas Posluszny, Joel A. Silberman | 2005-09-06 |
| 6924802 | Efficient function interpolation using SIMD vector permute functionality | Gordon Clyde Fossum, Barry L. Minor, Mark Richard Nutter | 2005-08-02 |
| 6915506 | Method and apparatus for evaluating results of multiple software tools | Sang Hoo Dhong, Sam Dinkin, Stephen Douglas Posluszny | 2005-07-05 |
| 6907477 | Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors | Erik R. Altman, Peter G. Capek, Michael K. Gschwind, James Allan Kahle, Ravi Nair +2 more | 2005-06-14 |
| 6865631 | Reduction of interrupts in remote procedure calls | Ravi Nair | 2005-03-08 |
| 6839828 | SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode | Michael K. Gschwind, Martin E. Hopkins | 2005-01-04 |
| 6836849 | Method and apparatus for controlling power and performance in a multiprocessing system according to customer level operational requirements | Bishop Brock, Mark A. Johnson, Thomas Walter Keller, Kevin John Nowka | 2004-12-28 |
| 6826110 | Cell circuit for multiport memory using decoder | Sang Hoo Dhong, Shoji Onishi, Osamu Takahashi | 2004-11-30 |