Issued Patents All Time
Showing 251–273 of 273 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6055554 | Floating point binary quad word format multiply instruction unit | — | 2000-04-25 |
| 6049860 | Pipelined floating point stores | Christopher A. Krygowski | 2000-04-11 |
| 6044454 | IEEE compliant floating point unit | Christopher A. Krygowski, Timothy J. Slegel, David F. McManigal, Mark S. Farrell | 2000-03-28 |
| 6021422 | Partitioning of binary quad word format multiply instruction on S/390 processor | — | 2000-02-01 |
| 6009261 | Preprocessing of stored target routines for emulating incompatible instructions on a target processor | Casper A. Scalzi, William J. Starke, James R. Urquhart, Douglas W. Westcott | 1999-12-28 |
| 5903479 | Method and system for executing denormalized numbers | Bruce C. Giamei, Christopher A. Krygowski, Mark A. Check, John S. Liptay | 1999-05-11 |
| 5764555 | Method and system of rounding for division or square root: eliminating remainder calculation | Thomas Joseph McPherson | 1998-06-09 |
| 5757682 | Parallel calculation of exponent and sticky bit during normalization | Robert M. Bunce, Leon Sigal, Hung C. Ngo | 1998-05-26 |
| 5742536 | Parallel calculation of exponent and sticky bit during normalization | Robert M. Bunce, Leon Sigal, Hung C. Ngo | 1998-04-21 |
| 5742535 | Parallel calculation of exponent and sticky bit during normalization | Robert M. Bunce, Leon Sigal, Hung C. Ngo | 1998-04-21 |
| 5737255 | Method and system of rounding for quadratically converging division or square root | — | 1998-04-07 |
| 5729481 | Method and system of rounding for quadratically converging division or square root | — | 1998-03-17 |
| 5687106 | Implementation of binary floating point using hexadecimal floating point unit | Charles F. Webb, Kai-Ann Ho | 1997-11-11 |
| 5654911 | Carry select and input select adder for late arriving data | Robert M. Bunce | 1997-08-05 |
| 5627774 | Parallel calculation of exponent and sticky bit during normalization | Robert M. Bunce, Leon Sigal, Hung C. Ngo | 1997-05-06 |
| 5619443 | Carry select and input select adder for late arriving data | Robert M. Bunce | 1997-04-08 |
| 5187679 | Generalized 7/3 counters | Stamatis Vassiliadis | 1993-02-16 |
| 4926371 | Two's complement multiplication with a sign magnitude multiplier | Stamatis Vassiliadis, Baik-Min Sung | 1990-05-15 |
| 4924424 | Parity prediction for binary adders with selection | Stamatis Vassiliadis, Michael Putrino, Brice J. Feal | 1990-05-08 |
| 4924423 | High speed parity prediction for binary adders using irregular grouping scheme | Stamatis Vassiliadis | 1990-05-08 |
| 4918639 | Overlapped multiple-bit scanning multiplication system with banded partial product matrix | Stamatis Vassiliadis | 1990-04-17 |
| 4916652 | Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures | Stamatis Vassiliadis | 1990-04-10 |
| 4225244 | Device for indicating fibre length distribution of a fibre sample | — | 1980-09-30 |