Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8395963 | Data security for dynamic random access memory at power-up | Todd A. Christensen, Travis R. Hebig, Daniel Mark Nelson | 2013-03-12 |
| 8344782 | Method and apparatus to limit circuit delay dependence on voltage for single phase transition | Todd A. Christensen, Travis R. Hebig, Daniel Mark Nelson | 2013-01-01 |
| 8159260 | Delay chain burn-in for increased repeatability of physically unclonable functions | Todd A. Christensen, Travis R. Hebig, Daniel Mark Nelson | 2012-04-17 |
| 8108739 | High-speed testing of integrated devices | Chad A. Adams, Todd A. Christensen, Travis R. Hebig | 2012-01-31 |
| 7971164 | Assessing resources required to complete a VLSI design | Travis R. Hebig, Daniel Mark Nelson, Jesse D. Smith | 2011-06-28 |
| 7924633 | Implementing boosted wordline voltage in memories | Todd A. Christensen, Travis R. Hebig, Daniel Mark Nelson | 2011-04-12 |
| 7911827 | Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels | Travis R. Hebig, Daniel Mark Nelson, Jesse D. Smith | 2011-03-22 |
| 7788554 | Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation | Chad A. Adams, Travis R. Hebig, Daniel Mark Nelson | 2010-08-31 |
| 7768851 | Apparatus for implementing SRAM cell write performance evaluation | Chad A. Adams, Travis R. Hebig, Daniel Mark Nelson | 2010-08-03 |
| 7751266 | High performance read bypass test for SRAM circuits | Chad A. Adams, Daniel Mark Nelson, Jeffrey M. Scherer | 2010-07-06 |
| 7737757 | Low power level shifting latch circuits with gated feedback for high speed integrated circuits | Travis R. Hebig, Daniel Mark Nelson, Jesse D. Smith | 2010-06-15 |
| 7724585 | Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability | Travis R. Hebig, Daniel Mark Nelson, Jesse D. Smith | 2010-05-25 |
| 7714630 | Method and apparatus to limit circuit delay dependence on voltage | Todd A. Christensen, Travis R. Hebig, Daniel Mark Nelson | 2010-05-11 |
| 7681095 | Methods and apparatus for testing integrated circuits | Peter Thomas Freiburger, Ryan Charles Kivimagi | 2010-03-16 |
| 7675794 | Design structure for improving performance of SRAM cells, SRAM cell, SRAM array, and write circuit | Sebastian Ehrenreich, Juergen Pille, Otto Wagner | 2010-03-09 |
| 7626851 | Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuit | Sebastian Ehrenreich, Juergen Pille, Otto Wagner | 2009-12-01 |
| 7535776 | Circuit for improved SRAM write around with reduced read access penalty | Travis R. Hebig, Daniel Mark Nelson, Jesse D. Smith | 2009-05-19 |
| 7525367 | Method for implementing level shifter circuits for integrated circuits | Todd A. Christensen, Travis R. Hebig | 2009-04-28 |
| 7505340 | Method for implementing SRAM cell write performance evaluation | Chad A. Adams, Travis R. Hebig, Daniel Mark Nelson | 2009-03-17 |
| 7502276 | Method and apparatus for multi-word write in domino read SRAMs | Todd A. Christensen, Travis R. Hebig, Daniel Mark Nelson | 2009-03-10 |
| 7443744 | Method for reducing wiring and required number of redundant elements | Peter Thomas Freiburger, Ryan Charles Kivimagi, Daniel Mark Nelson | 2008-10-28 |
| 7418637 | Methods and apparatus for testing integrated circuits | Peter Thomas Freiburger, Ryan Charles Kivimagi | 2008-08-26 |
| 7400550 | Delay mechanism for unbalanced read/write paths in domino SRAM arrays | Chad A. Adams, Anthony Gus Aipperspach, George Paulik | 2008-07-15 |
| 7283411 | Flood mode implementation for continuous bitline local evaluation circuit | Chad A. Adams, Ryan Charles Kivimagi | 2007-10-16 |
| 7224594 | Glitch protect valid cell and method for maintaining a desired state value | Chad A. Adams, Ryan Charles Kivimagi, Anthony Gus Aipperspach, Robert N. Krentler | 2007-05-29 |