Issued Patents All Time
Showing 51–70 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6943405 | Integrated circuit having pairs of parallel complementary FinFETs | Andres Bryant, William F. Clark, Jr., Mark D. Jaffe, Edward J. Nowak, John J. Pekarik +1 more | 2005-09-13 |
| 6934671 | Method and system for including parametric in-line test data in simulations for improved model to hardware correlation | John E. Bertsch, Daniel S. Coops | 2005-08-23 |
| 6888187 | DRAM cell with enhanced SER immunity | Jeffrey S. Brown, Edward J. Nowak, Beth Ann Rainey | 2005-05-03 |
| 6864136 | DRAM cell with enhanced SER immunity | Jeffrey S. Brown, Edward J. Nowak, Beth Ann Rainey | 2005-03-08 |
| 6849884 | Strained Fin FETs structure and method | William F. Clark, Jr., Louis D. Lanzerotti, Edward J. Nowak | 2005-02-01 |
| 6815277 | Method for fabricating multiple-plane FinFET CMOS | Edward J. Nowak | 2004-11-09 |
| 6812075 | Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same | Timothy J. Hoague, Edward J. Nowak, Jed H. Rankin | 2004-11-02 |
| 6800905 | Implanted asymmetric doped polysilicon gate FinFET | Edward J. Nowak, Jed H. Rankin | 2004-10-05 |
| 6767793 | Strained fin FETs structure and method | William F. Clark, Jr., Louis D. Lanzerotti, Edward J. Nowak | 2004-07-27 |
| 6750487 | Dual double gate transistor | Edward J. Nowak | 2004-06-15 |
| 6720231 | Fin-type resistors | Edward J. Nowak | 2004-04-13 |
| 6664582 | Fin memory cell and method of fabrication | Edward J. Nowak, Beth Ann Rainey | 2003-12-16 |
| 6662350 | FinFET layout generation | William C. Leipold, Edward J. Nowak | 2003-12-09 |
| 6657252 | FinFET CMOS with NVRAM capability | Chung H. Lam, Edward J. Nowak | 2003-12-02 |
| 6657259 | Multiple-plane FinFET CMOS | Edward J. Nowak | 2003-12-02 |
| 6642090 | Fin FET devices from bulk semiconductor and method for forming | Edward J. Nowak, Beth Ann Rainey, Devendra K. Sadana | 2003-11-04 |
| 6635909 | Strained fin FETs structure and method | William F. Clark, Jr., Louis D. Lanzerotti, Edward J. Nowak | 2003-10-21 |
| 6624651 | Kerf circuit for modeling of BEOL capacitances | Peter A. Habitz | 2003-09-23 |
| 6583469 | Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same | Timothy J. Hoague, Edward J. Nowak, Jed H. Rankin | 2003-06-24 |
| 6546303 | Computation of supply chain planning process efficiency | Thomas A. May | 2003-04-08 |