Issued Patents All Time
Showing 51–75 of 147 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9755701 | Hybrid tag for radio frequency identification system | Duixian Liu, Mihai A. Sanduleanu | 2017-09-05 |
| 9734371 | Hybrid tag for radio frequency identification system | Duixian Liu, Mihai A. Sanduleanu | 2017-08-15 |
| 9735732 | Coupled oscillators | Mark A. Ferriss, Wooram Lee, Bodhisatwa Sadhu, Alberto Valdes Garcia | 2017-08-15 |
| 9537224 | Phased-array transceiver | Xiaoxiong Gu, Duixian Liu, Arun Natarajan, Scott K. Reynolds, Alberto Valdes Garcia | 2017-01-03 |
| 9460383 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Yong Liu, Dharmendra S. Modha +4 more | 2016-10-04 |
| 9401696 | Boosting varactor capacitance ratio | Mark A. Ferriss, Bodhisatwa Sadhu, Alberto Valdes-Garcia | 2016-07-26 |
| 9373073 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation | John V. Arthur, Bernard V. Brezzo, Leland Chang, Paul A. Merolla, Dharmendra S. Modha +3 more | 2016-06-21 |
| 9337852 | Removing deterministic phase errors from fractional-N PLLs | Herschel A. Ainspan, Mark A. Ferriss, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes Garcia | 2016-05-10 |
| 9325331 | Prediction based digital control for fractional-N PLLs | Herschel A. Ainspan, Mark A. Ferriss, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes Garcia | 2016-04-26 |
| 9325332 | Adjusting the magnitude of a capacitance of a digitally controlled circuit | Herschel A. Ainspan, Mark A. Ferriss, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes-Garcia | 2016-04-26 |
| 9300246 | Resonator having distributed transconductance elements | Mark A. Ferriss, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes Garcia | 2016-03-29 |
| 9269042 | Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices | Seongwon Kim, Chung H. Lam, Dharmendra S. Modha, Bipin Rajendran, Jose A. Tierno | 2016-02-23 |
| 9240789 | Sub-rate low-swing data receiver | Yong Liu, Jose A. Tierno | 2016-01-19 |
| 9239984 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | John V. Arthur, Bernard V. Brezzo, Leland Chang, Paul A. Merolla, Dharmendra S. Modha +3 more | 2016-01-19 |
| 9231605 | Removing deterministic phase errors from fractional-N PLLS | Herschel A. Ainspan, Mark A. Ferriss, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes Garcia | 2016-01-05 |
| 9225348 | Prediction based digital control for fractional-N PLLs | Herschel A. Ainspan, Mark A. Ferriss, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes Garcia | 2015-12-29 |
| 9207695 | Calibration schemes for charge-recycling stacked voltage domains | Yong Liu, Jose A. Tierno | 2015-12-08 |
| 9203159 | Phased-array transceiver | Xiaoxiong Gu, Duixian Liu, Arun Natarajan, Scott K. Reynolds, Alberto Valdes Garcia | 2015-12-01 |
| 8913655 | Feed-forward equalizer architectures | Ankur Agrawal, John F. Bulzacchelli, Zeynep Toprak Deniz | 2014-12-16 |
| 8898097 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Yong Liu, Dharmendra S. Modha +4 more | 2014-11-25 |
| 8856055 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Yong Liu, Dharmendra S. Modha +4 more | 2014-10-07 |
| 8841893 | Dual-loop voltage regulator architecture with high DC accuracy and fast response time | John F. Bulzacchelli, Carrie E. Cox, Zeynep Toprak-Deniz, Joseph A. Iadanza, Todd M. Rasmus | 2014-09-23 |
| 8797084 | Calibration schemes for charge-recycling stacked voltage domains | Yong Liu, Jose A. Tierno | 2014-08-05 |
| 8779865 | Ultra-compact PLL with wide tuning range and low noise | Herschel A. Ainspan, John F. Bulzacchelli, Ankush Goel, Alexander V. Rylyakov | 2014-07-15 |
| 8774228 | Timing recovery method and apparatus for an input/output bus with link redundancy | John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, Sergey V. Rylov | 2014-07-08 |