Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9298395 | Memory system connector | Paul W. Coteus, Shawn A. Hall, Hillery C. Hunter, Douglas J. Joseph, Kyu-hyoun Kim +2 more | 2016-03-29 |
| 9263157 | Detecting defective connections in stacked memory devices | Warren E. Maule, Saravanan Sethuraman | 2016-02-16 |
| 9251894 | Accessing a resistive memory storage device | Kyu-hyoun Kim, Warren E. Maule | 2016-02-02 |
| 9189327 | Error-correcting code distribution for memory systems | Paul W. Coteus, Hillery C. Hunter, Kyu-hyoun Kim, Warren E. Maule, Kenneth L. Wright | 2015-11-17 |
| 9159410 | Accessing a resistive memory storage device | Kyu-hyoun Kim, Warren E. Maule | 2015-10-13 |
| 9146882 | Securing the contents of a memory device | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Kyu-hyoun Kim, Luis A. Lastras-Montano +1 more | 2015-09-29 |
| 9146883 | Securing the contents of a memory device | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Kyu-hyoun Kim, Luis A. Lastras-Montano +1 more | 2015-09-29 |
| 9087612 | DRAM error detection, evaluation, and correction | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Kyu-hyoun Kim, Luis A. Lastras-Montano +1 more | 2015-07-21 |
| 9064602 | Implementing memory device with sub-bank architecture | Hillery C. Hunter, Kyu-hyoun Kim, Warren E. Maule | 2015-06-23 |
| 9058896 | DRAM refresh | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Kyu-hyoun Kim, Luis A. Lastras +1 more | 2015-06-16 |
| 9037930 | Managing errors in a DRAM by weak cell encoding | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Kyu-hyoun Kim, Luis A. Lastras-Montano +1 more | 2015-05-19 |
| 9001609 | Hybrid latch and fuse scheme for memory repair | Michele M. Franceschini, Hillery C. Hunter, Kyu-hyoun Kim, Luis A. Lastras-Montano | 2015-04-07 |
| 8995217 | Hybrid latch and fuse scheme for memory repair | Michele M. Franceschini, Hillery C. Hunter, Kyu-hyoun Kim, Luis A. Lastras-Montano | 2015-03-31 |
| 8898544 | DRAM error detection, evaluation, and correction | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Kyu-hyoun Kim, Luis A. Lastras-Montano +1 more | 2014-11-25 |
| 8887014 | Managing errors in a DRAM by weak cell encoding | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Kyu-hyoun Kim, Luis A. Lastras-Montano +1 more | 2014-11-11 |
| 8848471 | Method for optimizing refresh rate for DRAM | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Kyu-hyoun Kim, Luis A. Lastras +1 more | 2014-09-30 |
| 8799566 | Memory system with a programmable refresh cycle | Kyu-hyoun Kim, Warren E. Maule, Vipin Patel | 2014-08-05 |
| 8659959 | Advanced memory device having improved performance, reduced power and increased reliability | Kyu-hyoun Kim, George Liang-Tai Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower +2 more | 2014-02-25 |
| 8452919 | Advanced memory device having improved performance, reduced power and increased reliability | Kyu-hyoun Kim, George Liang-Tai Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower +2 more | 2013-05-28 |
| 8307270 | Advanced memory device having improved performance, reduced power and increased reliability | Kyu-hyoun Kim, George Liang-Tai Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower +2 more | 2012-11-06 |
| 7984329 | System and method for providing DRAM device-level repair via address remappings external to the device | Luis A. Lastras-Montano, Darren L. Anand, Jeffrey H. Dreibelbis, Warren E. Maule, Robert B. Tremaine | 2011-07-19 |
| 7948817 | Advanced memory device having reduced power and improved performance | Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower, Hillery C. Hunter, Kyu-hyoun Kim +1 more | 2011-05-24 |
| 7717752 | 276-pin buffered memory module with enhanced memory system interconnect and features | Karl D. Loughner, Kevin C. Gower, Warren E. Maule | 2010-05-18 |
| 6799291 | Method and system for detecting a hard failure in a memory array | Shanker Singh | 2004-09-28 |
| 6785837 | Fault tolerant memory system utilizing memory arrays with hard error detection | Shanker Singh | 2004-08-31 |