Issued Patents All Time
Showing 51–73 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5555394 | Data processor with the ability of fast partial clearing of buffer memory | Fumio Arakawa | 1996-09-10 |
| 5454087 | Branching system for return from subroutine using target address in return buffer accessed based on branch type information in BHT | Susumu Narita, Fumio Arakawa, Hirokazu Aoki | 1995-09-26 |
| 5408625 | Microprocessor capable of decoding two instructions in parallel | Susumu Narita, Fumio Arakawa, Tetsuhiko Okada | 1995-04-18 |
| 5394558 | Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM | Fumio Arakawa, Susumu Narita | 1995-02-28 |
| 5386394 | Semiconductor memory device for performing parallel operations on hierarchical data lines | Takayuki Kawahara, Masakazu Aoki, Yoshinobu Nakagome, Makoto Hanawa, Masayuki Nakamura +2 more | 1995-01-31 |
| 5349672 | Data processor having logical address memories and purge capabilities | Tadahiko Nishimukai, Atsushi Hasegawa, Ikuya Kawasaki, Makoto Hanawa | 1994-09-20 |
| 5301285 | Data processor having two instruction registers connected in cascade and two instruction decoders | Makoto Hanawa, Osamu Nishii, Susumu Narita | 1994-04-05 |
| 5287484 | Multi-processor system for invalidating hierarchical cache | Osamu Nishii, Hirokazu Aoki, Takashi Kikuchi, Yasuhiko Saigou | 1994-02-15 |
| 5283886 | Multiprocessor cache system having three states for generating invalidating signals upon write accesses | Osamu Nishii, Hirokazu Aoki, Kanji Oishi, Jun Kitano, Susumu Hatano | 1994-02-01 |
| 5267198 | Static memory containing sense amp and sense amp switching circuit | Susumu Hatano, Kanji Oishi, Takashi Kikuchi, Yasuhiko Saigou, Hiroshi Fukuta +2 more | 1993-11-30 |
| 5206945 | Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses | Tadahiko Nishimukai, Atsushi Hasegawa, Ikuya Kawasaki, Makoto Hanawa | 1993-04-27 |
| 5202969 | Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively | Katsuyuki Sato, Tadahiko Nishimukai, Hirokazu Aoki, Susumu Hatano, Kanji Oishi +3 more | 1993-04-13 |
| 5193075 | Static memory containing sense AMP and sense AMP switching circuit | Susumu Hatano, Kanji Oishi, Takashi Kikuchi, Yasuhiko Saigou, Hiroshi Fukuta +2 more | 1993-03-09 |
| 5146573 | Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register | Katsuyuki Sato, Tadahiko Nishimukai, Hirokazu Aoki, Susumu Hatano, Kanji Oishi +3 more | 1992-09-08 |
| 5140681 | Multi-processing system and cache apparatus for use in the same | Hirokazu Aoki, Susumu Hatano, Kanji Oishi, Takashi Kikuchi, Hiroshi Fukuta +1 more | 1992-08-18 |
| 5129075 | Data processor with on-chip logical addressing and off-chip physical addressing | Tadahiko Nishimukai, Atsushi Hasegawa, Ikuya Kawasaki, Makoto Hanawa | 1992-07-07 |
| 4989140 | Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit | Tadahiko Nishimukai, Atsushi Hasegawa, Ikuya Kawasaki, Makoto Hanawa | 1991-01-29 |
| 4937738 | Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction | Atsushi Hasegawa, Takeshi Aimoto, Tadahiko Nishimukai | 1990-06-26 |
| 4912635 | System for reexecuting branch instruction without fetching by storing target instruction control information | Tadahiko Nishimukai, Atsushi Hasegawa, Yoshifumi Takamoto | 1990-03-27 |
| 4803616 | Buffer memory | Tadahiko Nishimukai, Atsushi Hasegawa | 1989-02-07 |
| 4797816 | Virtual memory supported processor having restoration circuit for register recovering | Tadahiko Nishimukai | 1989-01-10 |
| 4720811 | Microprocessor capable of stopping its operation at any cycle time | Noboru Yamaguchi, Haruo Koizumi, Yoshimune Hagiwara, Tadahiko Nishimukai | 1988-01-19 |
| 4646271 | Content addressable memory having dual access modes | Tadahiko Nishimukai | 1987-02-24 |