Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6199144 | Method and apparatus for transferring data in a computer system | Judge K. Arora, William R. Bryg, Stephen G. Burger, Gary N. Hammond | 2001-03-06 |
| 6182176 | Queue-based predictive flow control mechanism | Robert J. Brooks, William R. Bryg, Craig R. Frink, Thomas R. Hotchkiss, Robert D. Odineal +2 more | 2001-01-30 |
| 6128706 | Apparatus and method for a load bias--load with intent to semaphore | William R. Bryg, Stephen G. Burger, Gary N. Hammond | 2000-10-03 |
| 5784708 | Translation mechanism for input/output addresses | K. Monroe Bridges, Robert J. Brooks, William R. Bryg, Stephen G. Burger | 1998-07-21 |
| 5737757 | Cache tag system for use with multiple processors including the most recently requested processor identification | Joseph H. Hassoun, Robert D. Odineal | 1998-04-07 |
| 5586297 | Partial cache line write transactions in a computing system with a write back cache | William R. Bryg, Robert J. Brooks, Eric Hamilton | 1996-12-17 |
| 5535352 | Access hints for input/output address translation mechanisms | K. Monroe Bridges, Robert J. Brooks, William R. Bryg, Stephen G. Burger, Eric Hamilton +2 more | 1996-07-09 |
| 5530933 | Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus | Craig R. Frink, William R. Bryg, Kenneth K. Chan, Thomas R. Hotchkiss, Robert D. Odineal +1 more | 1996-06-25 |
| 5528766 | Multiple arbitration scheme | John F. Shelton, William R. Bryg | 1996-06-18 |
| 5519838 | Fast pipelined distributed arbitration scheme | Robert J. Brooks, William R. Bryg, Kenneth K. Chan, Thomas R. Hotchkiss, Robert E. Naas +4 more | 1996-05-21 |
| 5515522 | Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache | K. Monroe Bridges, William R. Bryg, Stephen G. Burger, James M. Hull | 1996-05-07 |
| 5133059 | Computer with multiple processors having varying priorities for access to a multi-element memory | Robert Fredieu, Heather D. Achilles | 1992-07-21 |
| 4794521 | Digital computer with cache capable of concurrently handling multiple accesses from parallel processors | Jonathan S. Blau, Robert Fredieu | 1988-12-27 |
| 4783736 | Digital computer with multisection cache | Robert Fredieu | 1988-11-08 |
| 4622630 | Data processing system having unique bus control protocol | Chandra Vora, Mark O. Bagula, Steve R. Hamilton | 1986-11-11 |
| 4513372 | Universal memory | Peter G. Marshall, David L. Whipple | 1985-04-23 |
| 4493033 | Dual port cache with interleaved read accesses during alternate half-cycles and simultaneous writing | Michael B. Druke | 1985-01-08 |
| 4398243 | Data processing system having a unique instruction processor system | Kenneth D. Holberger, James E. Veres, Carl S. Henry | 1983-08-09 |
| 4386399 | Data processing system | Edward Rasala, Steven Jeffrey Wallach, Carl J. Alsing, Kenneth D. Holberger, Charles J. Holland +4 more | 1983-05-31 |
| 4380812 | Refresh and error detection and correction technique for a data processing system | Michael B. Druke, John R. Van Roekel, Ward Baxter, II | 1983-04-19 |