Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11763881 | Computational memory cell and processing array device using the memory cells for XOR and XNOR computations | Eli Ehrman | 2023-09-19 |
| 11227653 | Storage array circuits and methods for computational memory cells | Park Soon-Kyu, Paul M-Bhor Chiang | 2022-01-18 |
| 11194548 | Processing array device that performs one cycle full adder operation and bit line read/write logic features | Bob Haig, Chao-Hung Chang | 2021-12-07 |
| 11150903 | Computational memory cell and processing array device using memory cells | Chao-Hung Chang, Avidan Akerib | 2021-10-19 |
| 10998040 | Computational memory cell and processing array device using the memory cells for XOR and XNOR computations | Eli Ehrman | 2021-05-04 |
| 10958272 | Computational memory cell and processing array device using complementary exclusive or memory cells | Avidan Akerib | 2021-03-23 |
| 10943648 | Ultra low VDD memory cell with ratioless write port | Patrick Chuang, Chao-Hung Chang | 2021-03-09 |
| 10930341 | Processing array device that performs one cycle full adder operation and bit line read/write logic features | Bob Haig, Chao-Hung Chang | 2021-02-23 |
| 10877731 | Processing array device that performs one cycle full adder operation and bit line read/write logic features | Bob Haig, Chao-Hung Chang | 2020-12-29 |
| 10860318 | Computational memory cell and processing array device using memory cells | Chao-Hung Chang, Avidan Akerib | 2020-12-08 |
| 10854284 | Computational memory cell and processing array device with ratioless write port | Patrick Chuang, Chao-Hung Chang | 2020-12-01 |
| 10725777 | Computational memory cell and processing array device using memory cells | Chao-Hung Chang, Avidan Akerib | 2020-07-28 |
| 10720205 | Systems and methods involving multi-bank, dual-pipe memory circuitry | Mu-Hsiang Huang, Robert Haig, Patrick Chuang | 2020-07-21 |
| 10535381 | Systems and methods of pipelined output latching involving synchronous memory arrays | Yoshinori Sato | 2020-01-14 |
| 10521229 | Computational memory cell and processing array device using memory cells | Chao-Hung Chang, Avidan Akerib | 2019-12-31 |
| 10303629 | Systems and methods involving data bus inversion memory circuitry, configuration(s) and/or operation | — | 2019-05-28 |
| 10249362 | Computational memory cell and processing array device using the memory cells for XOR and XNOR computations | Eli Ehrman | 2019-04-02 |
| 10192592 | Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features | Paul M-Bhor Chiang, Soon Kyu PARK, Gi-Won Cha | 2019-01-29 |
| 9966118 | Systems and methods of pipelined output latching involving synchronous memory arrays | Yoshinori Sato | 2018-05-08 |
| 9847111 | Systems and methods of pipelined output latching involving synchronous memory arrays | Yoshinori Sato | 2017-12-19 |
| 9613684 | Systems and methods involving propagating read and write address and data through multi-bank memory circuitry | Robert Haig | 2017-04-04 |
| 9613670 | Memory systems and methods involving high speed local address circuitry | Patrick Chuang, Mu-Hsiang Huang | 2017-04-04 |
| 9412440 | Systems and methods of pipelined output latching involving synchronous memory arrays | Yoshinori Sato | 2016-08-09 |
| 9384822 | Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features | Paul M-Bhor Chiang, Soon Kyu PARK, Gi-Won Cha | 2016-07-05 |
| 9385032 | Systems and methods involving data bus inversion memory circuitry, configuration and/or operation | — | 2016-07-05 |