| 11409528 |
Orthogonal data transposition system and method during data transfers to/from a processing array |
Bob Haig, Chih-Chiang Tseng, Mu-Hsiang Huang |
2022-08-09 |
$1,042,000 |
| 11194519 |
Results processing circuits and methods associated with computational memory cells |
Bob Haig, Eli Ehrman, Dan Ilan, Chao-Hung Chang, Mu-Hsiang Huang |
2021-12-07 |
$657,000 |
| 10943648 |
Ultra low VDD memory cell with ratioless write port |
Lee-Lean Shu, Chao-Hung Chang |
2021-03-09 |
$1,256,000 |
| 10891076 |
Results processing circuits and methods associated with computational memory cells |
Bob Haig, Eli Ehrman, Dan Ilan, Chao-Hung Chang, Mu-Hsiang Huang |
2021-01-12 |
$1,332,000 |
| 10860320 |
Orthogonal data transposition system and method during data transfers to/from a processing array |
Bob Haig, Chih-Chiang Tseng, Mu-Hsiang Huang |
2020-12-08 |
$1,243,000 |
| 10854284 |
Computational memory cell and processing array device with ratioless write port |
Chao-Hung Chang, Lee-Lean Shu |
2020-12-01 |
$2,352,000 |
| 10770133 |
Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits |
Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang |
2020-09-08 |
|
| 10720205 |
Systems and methods involving multi-bank, dual-pipe memory circuitry |
Mu-Hsiang Huang, Robert Haig, Lee-Lean Shu |
2020-07-21 |
$1,761,000 |
| 10659058 |
Systems and methods involving lock loop circuits, distributed duty cycle correction loop circuitry |
Yu-Chi Cheng |
2020-05-19 |
$1,889,000 |
| 10425070 |
Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry |
Yu-Chi Cheng, Jae Hyeong Kim |
2019-09-24 |
$1,775,000 |
| 9935635 |
Systems and methods involving pseudo complementary output buffer circuitry/schemes, power noise reduction and/or other features |
Jae Hyeong Kim, Chih-Chiang Tseng |
2018-04-03 |
$1,460,000 |
| 9853633 |
Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry |
Yu-Chi Cheng, Jae Hyeong Kim |
2017-12-26 |
$939,000 |
| 9679631 |
Systems and methods involving multi-bank, dual- or multi-pipe SRAMs |
Robert Haig, Chih-Chiang Tseng, Mu-Hsiang Huang |
2017-06-13 |
$1,701,000 |
| 9613670 |
Memory systems and methods involving high speed local address circuitry |
Mu-Hsiang Huang, Lee-Lean Shu |
2017-04-04 |
$808,000 |
| 9494647 |
Systems and methods involving data inversion devices, circuitry, schemes and/or related aspects |
Mu-Hsiang Huang, Jae Hyeong Kim |
2016-11-15 |
$859,000 |
| 9318174 |
Memory systems and methods involving high speed local address circuitry |
Mu-Hsiang Huang, Lee-Lean Shu |
2016-04-19 |
$730,000 |
| 9196324 |
Systems and methods involving multi-bank, dual- or multi-pipe SRAMs |
Robert Haig, Chih-Chiang Tseng, Mu-Hsiang Huang |
2015-11-24 |
$666,000 |
| 8982649 |
Systems and methods involving multi-bank, dual- or multi-pipe SRAMs |
Robert Haig, Chih-Chiang Tseng, Mu-Hsiang Huang |
2015-03-17 |
$1,112,000 |
| 8542050 |
Minimized line skew generator |
Jae Hyeong Kim, Chungji Lu |
2013-09-24 |
$172,000 |
| 7646215 |
Efficient method for implementing programmable impedance output drivers and programmable input on die termination on a bi-directional data bus |
Robert Haig, Chih-Chiang Tseng, Kookhwan Kwon |
2010-01-12 |
$1,011,000 |
| 7595657 |
Dynamic dual control on-die termination |
Robert Haig |
2009-09-29 |
$1,016,000 |
| 7389457 |
Shift registers free of timing race boundary scan registers with two-phase clock control |
Hsin-Ley Suzanne Chen, Michelle Huang |
2008-06-17 |
$1,309,000 |
| 7313040 |
Dynamic sense amplifier for SRAM |
Mu-Hsiang Huang, Jae Hyeong Kim |
2007-12-25 |
|
| 6798687 |
System and method for effectively implementing a high speed DRAM device |
Kuoyuan (Peter) Hsu, Gary Chang |
2004-09-28 |
$485,000 |
| 6078531 |
Word line voltage supply circuit |
Yoshifumi Miyazima, Hisanobu Tsukazaki |
2000-06-20 |
$2,446,000 |
