Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11409528 | Orthogonal data transposition system and method during data transfers to/from a processing array | Bob Haig, Patrick Chuang, Chih-Chiang Tseng | 2022-08-09 |
| 11257540 | Write data processing methods associated with computational memory cells | Bob Haig, Eli Ehrman, Chao-Hung Chang | 2022-02-22 |
| 11205476 | Read data processing circuits and methods associated with computational memory cells | Bob Haig, Eli Ehrman, Chao-Hung Chang | 2021-12-21 |
| 11194519 | Results processing circuits and methods associated with computational memory cells | Bob Haig, Eli Ehrman, Dan Ilan, Patrick Chuang, Chao-Hung Chang | 2021-12-07 |
| 11094374 | Write data processing circuits and methods associated with computational memory cells | Bob Haig, Eli Ehrman, Chao-Hung Chang | 2021-08-17 |
| 10891076 | Results processing circuits and methods associated with computational memory cells | Bob Haig, Eli Ehrman, Dan Ilan, Patrick Chuang, Chao-Hung Chang | 2021-01-12 |
| 10860320 | Orthogonal data transposition system and method during data transfers to/from a processing array | Bob Haig, Patrick Chuang, Chih-Chiang Tseng | 2020-12-08 |
| 10847213 | Write data processing circuits and methods associated with computational memory cells | Bob Haig, Eli Ehrman, Chao-Hung Chang | 2020-11-24 |
| 10847212 | Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers | Bob Haig, Eli Ehrman, Chao-Hung Chang | 2020-11-24 |
| 10777262 | Read data processing circuits and methods associated memory cells | Bob Haig, Eli Ehrman, Chao-Hung Chang | 2020-09-15 |
| 10770133 | Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits | Bob Haig, Eli Ehrman, Patrick Chuang, Chao-Hung Chang | 2020-09-08 |
| 10720205 | Systems and methods involving multi-bank, dual-pipe memory circuitry | Robert Haig, Patrick Chuang, Lee-Lean Shu | 2020-07-21 |
| 9679631 | Systems and methods involving multi-bank, dual- or multi-pipe SRAMs | Robert Haig, Patrick Chuang, Chih-Chiang Tseng | 2017-06-13 |
| 9613670 | Memory systems and methods involving high speed local address circuitry | Patrick Chuang, Lee-Lean Shu | 2017-04-04 |
| 9494647 | Systems and methods involving data inversion devices, circuitry, schemes and/or related aspects | Patrick Chuang, Jae Hyeong Kim | 2016-11-15 |
| 9318174 | Memory systems and methods involving high speed local address circuitry | Patrick Chuang, Lee-Lean Shu | 2016-04-19 |
| 9196324 | Systems and methods involving multi-bank, dual- or multi-pipe SRAMs | Robert Haig, Patrick Chuang, Chih-Chiang Tseng | 2015-11-24 |
| 8982649 | Systems and methods involving multi-bank, dual- or multi-pipe SRAMs | Robert Haig, Patrick Chuang, Chih-Chiang Tseng | 2015-03-17 |
| 7355907 | Performing read and write operations in the same cycle for an SRAM device | Hsin-Ley Suzanne Chen, Chih-Chiang Tseng | 2008-04-08 |
| 7313040 | Dynamic sense amplifier for SRAM | Jae Hyeong Kim, Patrick Chuang | 2007-12-25 |
| 7312629 | Programmable impedance control circuit calibrated at Voh, Vol level | Katsuya Nakashima, Yoshifumi Miyajima, Masahiro Ichihashi | 2007-12-25 |