Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9356611 | Systems and methods involving phase detection with adaptive locking/detection features | Jyn-Bang Shyu, Yoshinori Sato, Jae Hyeong Kim | 2016-05-31 |
| 9318174 | Memory systems and methods involving high speed local address circuitry | Patrick Chuang, Mu-Hsiang Huang | 2016-04-19 |
| 9135986 | Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features | Chenming W. Tung, Hsin You S. Lee | 2015-09-15 |
| 9053768 | Systems and methods of pipelined output latching involving synchronous memory arrays | Yoshinori Sato | 2015-06-09 |
| 9018992 | Systems and methods involving phase detection with adaptive locking/detection features | Jyn-Bang Shyu, Yoshinori Sato, Jae Hyeong Kim | 2015-04-28 |
| 8885439 | Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocks | Tuan Nguyen, William Le | 2014-11-11 |
| 8638144 | Systems and methods involving phase detection with adaptive locking/detection features | Jyn-Bang Shyu, Yoshinori Sato, Jae Hyeong Kim | 2014-01-28 |
| 8575982 | Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines | Jae Hyeong Kim, Jyn-Bang Shyu | 2013-11-05 |
| 8488408 | Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocks | Tuan Nguyen, William Le | 2013-07-16 |
| 8400200 | Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines | Jae Hyeong Kim, Jyn-Bang Shyu | 2013-03-19 |
| 8116161 | System and method for refreshing a DRAM device | Stephen Lee | 2012-02-14 |
| 7292490 | System and method for refreshing a DRAM device | Stephen Lee | 2007-11-06 |
| 6775193 | System and method for testing multiple embedded memories | Taiching Shyu | 2004-08-10 |
| 6762973 | Data coherent logic for an SRAM device | Chenming W. Tung, Stephen Lee | 2004-07-13 |
| 6295242 | SRAM with current-mode test read data path | Kurt Knorpp, Katsunori Seno | 2001-09-25 |
| 5519712 | Current mode test circuit for SRAM | Kurt Knorpp, Katsunori Seno | 1996-05-21 |
| 5457407 | Binary weighted reference circuit for a variable impedance output buffer | Kurt Knorpp | 1995-10-10 |
| 5384503 | SRAM with current-mode read data path | Kurt Knorpp, Katsunori Seno | 1995-01-24 |
| 5355343 | Static random access memory with self timed bit line equalization | Chenming W. Tung | 1994-10-11 |
| 4694205 | Midpoint sense amplification scheme for a CMOS DRAM | Tai-Ching Shyu | 1987-09-15 |
| 4670861 | CMOS N-well bias generator and gating system | Chao-Ven Kao, Tai-Ching Shyu | 1987-06-02 |
| 4634894 | Low power CMOS reference generator with low impedance driver | Tai-Ching Shyu, Patrick Chuang | 1987-01-06 |